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Efficient multi-standard cognitive radios on FPGAs 24

Efficient multi-standard cognitive radios on FPGAs

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24th international conference on field programmable logic and applications, FPL 2014

作者： Pham, thinh H. Fahmy, Suhaib A. McLoughlin, Ian Vince School of Computer Engineering Nanyang Technological University Singapore Singapore School of Information Science and Technology University of Science and Technology of China Hefei China

ISBN: (纸本)9783000446450

Cognitive radios that support multiple standards and modify operation depending on environmental conditions are becoming more important as the demand for higher bandwidth and efficient spectrum use increases. Traditional implementations in custom ASICs cannot support such flexibility, with standards changing at a faster pace, while software baseband implementations fail to achieve the performance required. Hence, FPGAs offer an ideal platform bringing together flexibility, performance, and efficiency. this work explores the possible techniques for designing multi-standard radios on FPGAs, and explores how partial reconfiguration can be leveraged in a way that is amenable for domain experts with minimal FPGA knowledge. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Experimental multi-FPGA GNSS receiver platform 24

Experimental multi-FPGA GNSS receiver platform

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Garzia, Fabio Rugamer, Alexander Koch, Robert Neumaier, Philipp Serezhkina, Ekaterina Overbeck, Matthias Rohmer, Gunther Fraunhofer IIS Nuremberg Germany

ISBN: (纸本)9783000446450

this paper describes the system architecture and implementation results of a robust and flexible dual-frequency 2×2 array processing GNSS receiver platform. A digital front-end FPGA pre-processes the incoming raw ADC data and implements interference mitigation methods in time and frequency domain. An optional second FPGA card can be used to realize more sophisticated and computational complex interference mitigation techniques. Finally, the data stream is processed on a baseband FPGA platform with spatial array processing techniques using a software assisted hardware GNSS receiver approach. the interconnection of the FPGAs is realized using gigabit transceivers handling a constant raw data rate of 16.8 Gbit/s. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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HPC-gSpan: An FPGA-based parallel system for frequent subgraph mining 24

HPC-gSpan: An FPGA-based parallel system for frequent subgra...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Stratikopoulos, Athanasios Chrysos, Grigorios Papaefstathiou, Ioannis Dollas, Apostolos Microprocessor and Hardware Laboratory Department of Electronic and Computer Engineering Technical University of Crete Chania Greece

ISBN: (纸本)9783000446450

Graph mining is an important research area within the domain of data mining. One of the most challenging tasks of graph mining is frequent subgraph mining. this work presents the first FPGA-based implementation, to the best of our knowledge, of the most efficient and well-known algorithm for the Frequent Subgraph Mining (FSM) problem, i.e. gSpan. the proposed system, named High Performance Computing-gSpan (HPC-gSpan), achieves manyfold speedup vs. the official software solution of the gboost library when executed on a high-end CPU for various real-world datasets. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Hardware conversion of neural networks simulation models for neural processing accelerator implemented as FPGA-based SoC 24

Hardware conversion of neural networks simulation models for...

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Pietras, Marcin Computer Science and Information Technology West Pomeranian University of Technology ZUT Szczecin Poland

ISBN: (纸本)9783000446450

the transition from a neural network simulation model to its hardware representation is a complex process, which touches computations precision, performance and effective architecture implementation issues. Presented neural processing accelerator involves neural network sectioning, precision reduction and weight coefficients parsing (arrangements) in order to increase efficiency and maximize FPGA hardware resources utilization. Particular attention has been devoted on to ANN conversion methods designed for a system based on neural processing units and related with this process redundant calculations and empty neurons generation. In addition, this paper describes the FPGA-based Neural Processing Accelerator architecture benchmark for real example implementation of a pattern recognition neural network. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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FlipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms 24

FlipSyrup: Cycle-accurate hardware simulation framework on a...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Takamaeda-Yamazaki, Shinya Kise, Kenji Nara Institute of Science and Technology Japan Tokyo Institute of Technology Japan

ISBN: (纸本)9783000446450

FPGA-based rapid prototyping is widely applied for fast simulations of hardware structure verifications. In this paper, we propose flipSyrup, a prototyping framework for cycle-accurate hardware simulations on abstract FPGA platforms. In order to mitigate the development complexity of FPGA-based simulators, the framework provides two abstractions of resources on FPGA platforms: Memory systems and inter-FPGA interconnections on multi-FPGA platforms. the framework enables designers to draw up a target hardware using abstract interfaces as ideal memory systems and interconnections on FPGA platforms. Our evaluation result shows that the slowdowns in simulation speed under the abstractions by using the framework are not critical. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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DyRACT: A partial reconfiguration enabled accelerator and test platform 24

DyRACT: A partial reconfiguration enabled accelerator and te...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Vipin, Kizheppatt Fahmy, Suhaib A. School of Computer Engineering Nanyang Technological University Singapore Singapore

ISBN: (纸本)9783000446450

Integrating FPGAs with a general purpose computer remains difficult, but recent efforts have resulted in open frameworks that offer a software API and hardware interface to allow easier integration. However, such systems only support static FPGA designs. With the addition of partial reconfiguration (PR) support, such frameworks can enable more effective use of FPGAs. Now, designers can incorporate hardware accelerators within their software applications, and these can be loaded dynamically as required. We present a PR-enabled FPGA platform that allows user modules to be loaded onto the FPGA, inputs to be applied, results obtained, and functions to be swapped at runtime. the interface and PR management logic are part of the static region, while multiple accelerators can be loaded using high level functions provided by the API. Reconfiguration and data transfer are both managed over the PCIe interface from the host PC, with communication throughput of more than 1.5 GB/s (75% of peak PCIe bandwidth) and reconfiguration of a large accelerator in 20 ms. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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An enhanced and embedded GNU radio flow 24

An enhanced and embedded GNU radio flow

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24th international conference on field programmable logic and applications, FPL 2014

作者： Marlow, Ryan Dobson, Chris Athanas, Peter Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University BlacksburgVA United States

ISBN: (纸本)9783000446450

this paper presents a Zynq capable version of GNU Radio - an open-source rapid radio deployment tool - with an enhanced flow that utilizes the processing capability of FPGAs. this work features TFlow - an FPGA back-end compilation accelerator for instant FPGA assembly. the Xilinx Zynq FPGA architecture integrates the FPGA fabric and CPU onto a single chip, which eliminates the need for a controlling host computer;thus, providing a single, portable, low-power, embedded platform. By exploiting the computational advantages of FPGAs in the GNU Radio flow, a larger class of software defined radios can be implemented. Once the FPGA is programmed with a design, modules can be parameterized to realize an even larger class of applications and further solidify the concept of rapid assembly of software defined radios. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Educating hardware design - From primary school children to postgraduate engineers 24

Educating hardware design - From primary school children to ...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Knodel, Oliver Zabel, Martin Lehmann, Patrick Spallek, Rainer G. Department of Computer Science Technische Universität Dresden Germany

ISBN: (纸本)9783000446450

the future of hardware development lies in massively parallel hardware architectures as used in embedded as well as high-performance systems, for instance streaming-based, real-time and database applications. Especially field-programmable gate arrays provide a platform for the rapid development of integrated circuits and the accompanied software. For reasons of energy efficiency, it is increasingly important to tailor hardware directly to the application. As such systems are very complex, the training of engineers has to start early. Furthermore, the usual curricula in computer science and electrical engineering teach only basic skills. Our approach does not start with specialized courses in master or diploma programs, but already with the motivation of primary school children for technical disciplines. Girls and boys are addressed equally. In school, children are made familiar with programmable circuits and thus motivated to study computer science with a specialization in computer engineering. In this paper we present our lectures and practical courses for bachelor and master students. With examples from final bachelor and master projects we demonstrate the quality of our education and its integration into current research. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Hierarchical reconfiguration of FPGAs 24

Hierarchical reconfiguration of FPGAs

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24th international conference on field programmable logic and applications, FPL 2014

作者： Koch, Dirk Beckhoff, Christian University of Manchester United Kingdom University of Oslo Norway

ISBN: (纸本)9783000446450

Partial reconfiguration allows some applications to substantially save FPGA area by time sharing resources among multiple modules. In this paper, we push this approach further by introducing hierarchical reconfiguration where reconfigurable modules can have reconfigurable submodules. this is useful for complex systems where many modules have common parts or where modules can share components. For such systems, we show that the number of bitstreams and the bitstream storage requirements can be scaled down from a multiplicative to an additive behavior with respect to the number of modules and submodules. A case study consisting of different reconfigurable softcore CPUs and hierarchically reconfigurable custom instruction set extensions demonstrates a 18.7× lower bitstream storage requirement and up to 10× faster reconfiguration speed when using hierarchical reconfiguration instead of using conventional single-level module-based reconfiguration. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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A survey of open source processors for FPGAs 24

A survey of open source processors for FPGAs

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24th international conference on field programmable logic and applications, FPL 2014

作者： Jia, Rui Lin, Colin Yu Guo, Zhenhong Chen, Rui Wang, Fei Gao, Tongqiang Yang, Haigang System on Programmable Chip Research Department Institute of Electronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783000446450

FPGA-based SoCs have been gaining great favors among traditional applications and expanding the application domains to some new areas. Reusing and sharing components is an attractive and pratical methodology for system designers to reduce the design complexity of the SoC architectures. Open source hardware has become an effective method of improving the design productivity. As the core functional component, processors affects the performance of SoC systems. this paper investigates existing open source processors, and gives an overview. From the points of usability and stability, the main features of open source processors are summarized. Following these features, some open source processors with high usability and stability are selected. these open source processors and existing vendor-provided soft processors are implemented on Stratix V and Virtex-7 FPGAs using corresponding EDA tools, Quart us n and ISE. the implementation results are compared and discussed. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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