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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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A survey of open source processors for FPGAs 24

A survey of open source processors for FPGAs

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Jia, Rui Lin, Colin Yu Guo, Zhenhong Chen, Rui Wang, Fei Gao, Tongqiang Yang, Haigang System on Programmable Chip Research Department Institute of Electronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783000446450

FPGA-based SoCs have been gaining great favors among traditional applications and expanding the application domains to some new areas. Reusing and sharing components is an attractive and pratical methodology for system designers to reduce the design complexity of the SoC architectures. Open source hardware has become an effective method of improving the design productivity. As the core functional component, processors affects the performance of SoC systems. this paper investigates existing open source processors, and gives an overview. From the points of usability and stability, the main features of open source processors are summarized. Following these features, some open source processors with high usability and stability are selected. these open source processors and existing vendor-provided soft processors are implemented on Stratix V and Virtex-7 FPGAs using corresponding EDA tools, Quart us n and ISE. the implementation results are compared and discussed. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Using high-level knowledge to enhance data channels in FPGA streaming systems 24

Using high-level knowledge to enhance data channels in FPGA ...

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Wijeyasinghe, Marlon thomas, David Department of Electrical and Electronic Engineering Imperial College London United Kingdom

ISBN: (纸本)9783000446450

FPGAs are commonly used in high performance computing applications, often in the form of streaming systems which exploit parallelism of algorithms along pipelined kernels. While such applications have traditionally been designed at the Register Transfer Level (RTL), the increasing complexity in terms of FPGA resource usage, arithmetic logic and dataflow is causing the time taken for RTL programming to be prohibitive. this necessitates using high-level programming tools to transpar-ently handle low-level aspects - thus simplifying the design pro-cess. Examples of high-level tools for building streaming systems include MaxCompiler by Maxeler Technologies and DSP Builder by Altera. We propose an interception layer which when inserted into communication channels, transparently enhances their per-formance and capabilities without needing to modify the stream-ing kernels or host code. We discuss specific channel enhance-ments: lossless compression to improve effective bandwidth;error correction and fault tolerance to improve reliability. the interception layer is intended to add complex behaviour while maintaining the simplicity of the high-level abstraction when transmitting data via a channel. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Improving FPGA accelerated tracking with multiple online trained classifiers 24

Improving FPGA accelerated tracking with multiple online tra...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Jacobsen, Matthew Sampangi, Siddarth Freund, Yoav Kastner, Ryan Computer Science and Engineering University of California San Diego United States

ISBN: (纸本)9783000446450

Robust real time tracking is a requirement for many emerging applications. Many of these applications must track objects even as their appearance changes. Training classifiers online has become an effective approach for dealing with variability in object appearance. Classifiers can learn and adapt to changes online at the cost of additional runtime computation. In this paper, we propose a FPGA accelerated design of an online boosting algorithm that uses multiple classifiers to track and recover objects in real time. Our algorithm uses a novel method for training and comparing pose-specific classifiers along with adaptive tracking classifiers. Our FPGA accelerated design is able to track at 60 frames per second while concurrently evaluating 11 classifiers. this represents a 30× speed up over a CPU based software implementation. It also demonstrates tracking accuracy at state of the art levels on a standard set of videos. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Aging effects in FPGAs: An experimental analysis 24

Aging effects in FPGAs: An experimental analysis

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Amouri, Abdulazim Bruguier, Florent Kiamehr, Saman Benoit, Pascal Torres, Lionel Tahoori, Mehdi Karlsruhe Germany LIRMM CNRS - University of Montpellier 2 161 rue Ada cedex 534095 France

ISBN: (纸本)9783000446450

Modern field programmable Gate Arrays (FPGAs) are built using the most advanced technology nodes to meet performance and power demands. this makes them susceptible to various reliability challenges at nano-scale, and in particular to transistor aging. In this paper, an experimental analysis is made to identify the main parameters and phenomena influencing the performance degradation of FPGAs. For that purpose, a set of controlled ring-oscillator-based sensors with different frequencies and tunable activity control are implemented on a Spartan-6 FPGA. thus, the internal switching activities (SAs) and signal probabilities (SPs) of the sensors can be varied. We performed accelerated-lifetime conditions using elevated temperatures and voltages in a controlled setting to stress the FPGA. A novel monitoring method based on measuring the electromagnetic emissions of the FPGA is used to accurately monitor the performance of the sensors before and after the stress. the experiments reveal the extent of performance degradations, the impact of SPs and SAs, and the relative impacts of BTI and HCI aging factors. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs 24

A bit-interleaved embedded hamming scheme to correct single-...

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Venkataraman, Shyamsundar Santos, Rui Das, Anup Kumar, Akash Department of Electrical and Computer Engineering National University of Singapore Singapore Singapore

ISBN: (纸本)9783000446450

Single Event Upsets (SEUs) inadvertently change the configuration bits of Static-RAM (SRAM)-based field programmable Gate Arrays (FPGAs), leading to erroneous output until the error has been corrected. Scrubbing using an Error Correction Code (ECC) such as hamming is a popular method to correct such faults. However, current works either require a large external memory to store the ECCs or can at most correct only one error in a frame. this paper proposes a novel bit-interleaved embedded hamming scheme along with scrubbing, to correct single (SBUs) and multi-bit upsets (MBUs) in SRAM-based FPGAs. this scheme does not require an external memory to store the ECCs, as they are embedded within the configuration memory itself. Experiments conducted on various benchmarks show that the proposed scheme can handle multiple errors per frame very well, with an embedding efficiency of over 99.3%. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Interconnect for commodity FPGA clusters: Standardized or customized? 24

Interconnect for commodity FPGA clusters: Standardized or cu...

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Markettos, A. theodore Fox, Paul J. Moore, Simon W. Moore, Andrew W. Computer Laboratory University of Cambridge United Kingdom

ISBN: (纸本)9783000446450

We demonstrate that a small library of customizable interconnect components permits low-area, high-performance, reliable communication tuned to an application, by analogy with the way designers customize their compute. Whilst soft cores for standard protocols (Ethernet, RapidIO, Infiniband, Interlaken) are a boon for FPGA-to-other-system interconnect, we argue that they are inefficient and unnecessary for FPGA-to-FPGA interconnect. Using the example of BlueLink, our lightweight pluggable interconnect library, we describe how to construct reliable FPGA clusters from hundreds of lower-cost commodity FPGA boards. Utilizing the increasing number of serial links on FPGAs demands efficient use of soft-logic, making domain-optimized custom interconnect attractive for some time to come. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Area implications of memory partitioning for high-level synthesis on FPGAs 24

Area implications of memory partitioning for high-level synt...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Gallo, Luca Cilardo, Alessandro thomas, David Bayliss, Samuel Constantinides, George A. University of Naples Federico II Via Claudio 21 Napoli80125 Italy Imperial College London LondonSW7 2BT United Kingdom

ISBN: (纸本)9783000446450

FPGAs normally have numerous independent memory banks that can be accessed simultaneously, potentially offering a very large memory bandwidth. Adopting a suitable application-based memory partitioning strategy is thus vital to take full advantage of the memory architecture. In addition to improving the potential memory bandwidth, partitioning also affects the area complexity of the generated system because the required steering logic depends on the partitioning scheme. this work describes the area implications of a lattice-based memory partitioning technique in the context of high-level synthesis for FPGAs. Experimental results with a commercial HLS tool show that the proposed partitioning technique improves area efficiency compared to alternative approaches. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs 24

High-level synthesis-based design methodology for Dynamic Po...

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Ahmed, Rehan Bsoul, Assem A. M. Wilton, Steven J. E. Hallschmid, Peter Klukas, Richard University of British Columbia Canada Blackcomb Design Automation Canada

ISBN: (纸本)9783000446450

Static leakage power consumption is critical in modern FPGAs for many applications. Dynamic Power-Gating (DPG), in which parts of the FPGA in-use logic blocks are powered-down at run-time, is a promising technique to reduce the static power. Adoption of such emerging DPG enabled FPGA architectures remains challenging as the current tool-chains to program the FPGA does not support this type of power-gating. Moreover, manually identifying profitable power-gating opportunities in an application requires significant design expertise and is time consuming. In this paper, we propose a high-level synthesis-based design framework that exploits the dynamic power-gating feature of the FPGAs to minimize the static power dissipation. We use this framework on a set of CHStone benchmark suite and demonstrate that power-gating opportunities for hardware accelerators can be identified in an automatic way. Results show that up to 96% reduction in static energy is achieved for individual accelerators using dynamic power-gating technique. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Asynchronously assisted FPGA for variability 24

Asynchronously assisted FPGA for variability

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24th international conference on field programmable logic and applications, FPL 2014

作者： Low, Hock S. Shang, Delong Xia, Fei Yakovlev, Alex Systems Design Group Newcastle University Newcastle upon Tyne United Kingdom

ISBN: (纸本)9783000446450

the effect of variability has become increasingly significant as a result of technology geometry scaling. this paper describes Asynchronous Assisting logic (AAL) blocks and the method of introducing them into modern FPGA architecture, in order to increase tolerance of the wide range latency variations caused by parametric variation, and temperature and supply voltage fluctuations. the proposed method leverages the availability of variation maps and suggests deploying configurable AAL blocks only into the variation critical paths - reinforcing rather rerouting/remapping. this method reduces the size overhead significantly which normally will be incurred by fully asynchronous designs. the proposed technique maintains the existing FPGA architecture allowing potential reuse of design flow. Simulations show correct functionality given regularly variable, randomly variable and capacitor switching energy harvester voltage supplies. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Achieving portability and efficiency over chip heterogeneous multiprocessor systems 24

Achieving portability and efficiency over chip heterogeneous...

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Cartwright, E. Sadeghian, Alborz Ma, Sen Andrews, David Dept. of Computer Science and Computer Engineering University of Arkansas Fayetteville United States

ISBN: (纸本)9783000446450

Emerging programming models for chip heterogeneous multiprocessor (CHMP) systems elevate architecture details up into the source code. this eliminates portability and requires designers to navigate a multidimensional search space when trying to optimize designs. In this paper, we present an approach that reinstates portability through a combination of polymorphic functions and an adaptive runtime system. Together they enable runtime profiling and dynamic scheduling of unaltered source code across systems with different combinations of heterogeneous resources. Our results verify the ability of our programming model and runtime system to re-enable the notion of writing code once and run anywhere. Runtime results show how runtime tuning can increase resource utilization and provide performance increases as the number and heterogeneity of computing resources increases. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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