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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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SoGraph: A State-Aware Architecture for Out-of-Memory Graph Processing on HBM-Equipped FPGAs

SoGraph: A State-Aware Architecture for Out-of-Memory Graph ...

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international conference on field programmable logic and applications

作者： Qianyu Cheng Zhendong Zheng Tianhao Jiang Cheng Tang Teng Wang Lei Gong Chao Wang Xuehai Zhou University of Science and Technology of China Hefei China Suzhou Institute for Advanced Research University of Science and Technology of China Suzhou China

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Emerging FPGA devices are widely used in graph processing and achieve high performance by exploiting fine-grained parallelism and high-bandwidth memory (HBM) sub-systems with dozens of channels. However, the graph size increases rapidly and often exceeds the capacity of the FPGA device or one of the memory channels, incurring out-of-memory (OoM) faults and performance degradation. Existing approaches focus on improving the performance of on-device full graph processing, ignoring the support for hyper-scale graphs and cross-iteration acceleration. In this work, we propose SoGraph, a graph processing architecture for large graph acceleration on HBM-equipped FPGAs, cooperating with the host. To minimize PCIe traffic during the processing, we adopt three hardware-oriented optimizations: 1) activeness-driven subgraph scheduler, which minimizes on-device graph resident set; 2) lightweight state-aware processing extension in edge-centric paradigm; 3) bit-level update analyzer for to-be-transfer subgraph reduction. the results show that the prototype on Alveo U280 FPGA achieves an average of 3.18x performance speedup over the modified state-of-the-art FPGA design and 1.3x energy efficiency over the GPU solution.

关键词： Performance evaluation Redundancy Memory management Prototypes Graphics processing units Parallel processing Energy efficiency logic field programmable gate arrays Optimization

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Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs

Shedding the Bits: Pushing the Boundaries of Quantization wi...

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international conference on field programmable logic and applications

作者： Shivam Aggarwal Hans Jakob Damsgaard Alessandro Pappalardo Giuseppe Franco thomas B. Preußer Michaela Blott Tulika Mitra School of Computing National University of Singapore Singapore AMD Research and Advanced Development Dublin Ireland Electrical Engineering Unit Tampere University Finland AMD Germany

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Post-training quantization (PTQ) is a powerful technique for model compression, reducing the numerical precision in neural networks without additional training overhead. Recent works have investigated adopting 8 -bit floating-point formats (FP8) in the context of PTQ for model inference. However, floating-point formats smaller than 8 bits and their relative comparison in terms of accuracy-hardware cost with integers remains unexplored on FPGAs. In this work, we present minifloats, which are reduced-precision floating-point formats capable of further reducing the memory footprint, latency, and energy cost of a model while approaching full-precision model accuracy. We implement a custom FPGA-based multiply-accumulate operator library and explore the vast design space, comparing minifloat and integer representations across 3 to 8 bits for both weights and activations. We also examine the applicability of various integer-based quantization techniques to minifloats. Our experiments show that minifloats offer a promising alternative for emerging workloads such as vision transformers.

关键词： Training Quantization (signal) Costs Accuracy Neural networks Transformers Data models Numerical models Resource management field programmable gate arrays

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KIT: Kernel Isotropic Transformation of Bilateral Filters for Image Denoising on FPGA

KIT: Kernel Isotropic Transformation of Bilateral Filters fo...

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international conference on field programmable logic and applications

作者： Fanny Spagnolo Pasquale Corsonello Fabio Frustaci Stefania Perri Department of Informatics Modelling Electronics and Systems Engineering Department of Mechanical Energy and Management Engineering University of Calabria Rende Italy

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

A Bilateral filter (BF) is commonly adopted as a pre-processing stage in several computer vision tasks because of its ability to denoise images. In contrast to the traditional image convolution that adopts a static kernel, a BF computes adaptive weights on-the-fly by applying exponentiation and division operations to the current pixel window. Prior works dealing with hardware acceleration of the BF rely on straightforward implementations that approximate the exponential function through look-up-tables (LUTs). this paper presents a new approximation technique to efficiently deploy a BF within real-time and low-energy intelligent systems based on FPGAs. the proposed strategy replaces the adaptive filter with its inexact isotropic version. this choice allows dropping a certain number of operations, thus resulting in enhanced speed and energy performances with respect to state-of-the-art hardware accelerators. When implemented on the AMD Xilinx Zynq XC7Z020 FPGA device, the proposed $5 \times 5$ BF design elaborates ∽237 Mega pixels per second and consumes at most 174 mW, with a Peak Signal-to-Noise Ratio (PSNR) degradation of just 0.55% at a noise standard deviation equal to 30.

关键词： Performance evaluation PSNR Noise Adaptive filters Real-time systems Table lookup Kernel field programmable gate arrays Hardware acceleration Standards

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Exploring the Versal AI Engines for Signal Processing in Radio Astronomy

Exploring the Versal AI Engines for Signal Processing in Rad...

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international conference on field programmable logic and applications

作者： Victor Van Wijhe Vincent Sprave Daniele Passaretti Nikolaos Alachiotis Gerrit Grutzeck thilo Pionteck Steven Van der Vlugt Netherlands Institute for Radio Astronomy (ASTRON) 7990 AA Dwingeloo The Netherlands Faculty of EEMCS University of Twente The Netherlands Otto-von-Guericke University Magdeburg Magdeburg Germany Max Planck Institute for Radio Astronomy Bonn Germany

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Nowadays, heterogeneous architectures are widely used to overcome the ongoing demand for increased computing performance at the edge, such as the pre-processing of raw antenna data in radio telescope systems. the Versal Adaptive SoC is a novel heterogeneous architecture that includes programmable logic (PL), a Processing System, and Artificial Intelligence Engines (AIEs) interconnected by a programmable Network-on-Chip. In this work, we explore the AIEs to evaluate their capabilities for real-time signal processing in radio telescope systems. We focus on the implementation of a Polyphase Filter Bank (PFB), which is a representative signal processing operation that consists of Finite Impulse Response (FIR) filters and the Fast-Fourier Transform (FFT) algorithm. We analyzed the performance of the AIEs with regard to the requirements of LOFAR, the world’s largest low-frequency radio telescope. By means of the roofline model, we reveal that the AIEs theoretically meet the LOFAR computational requirements, but the FIR vendor-provided library implementation did not reach the required performance. therefore, we explore several optimization strategies for the FIR implementation on the AIEs and analyze the communication options between the PL and the AIE array. Finally, we have developed an efficient PFB implementation that requires only 12 AIEs. A prototype on a VC1902 device achieves a throughput of 437 MSPS, which is more than sufficient for a single antenna polarization of the LOFAR system. this work is open source and publicly available at: https://***/rd/acap.

关键词： Performance evaluation Radio astronomy Finite impulse response filters Filter banks Computer architecture logic gates throughput Space exploration Antennas Engines

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BitBlender: Scalable Bloom Filter Acceleration on FPGAs with Dynamic Scheduling

BitBlender: Scalable Bloom Filter Acceleration on FPGAs with...

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international conference on field programmable logic and applications

作者： Kenneth Liu Alec Lu Zhenman Fang HiAccel Lab Simon Fraser University Burnaby B.C Canada

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

the Bloom filter is one of the most widely used data structures in big data analytics to efficiently filter out vast amounts of noisy data. Unfortunately, prior Bloom filter designs only focus on single-input-stream acceleration, and can no longer match the increasing data rates offered by modern *** support large Bloom filters with low false-positive rate and high throughput, we present BitBlender, a configurable and scalable multi-input-stream Bloom filter acceleration framework in HLS. To effectively share one large bit-vector on chip among all streams, we design and implement the novel arbiter and unshuffle modules to dynamically schedule conflicting accesses to execute sequentially and non-conflicting accesses to execute in parallel. To support different user configurations of the Bloom filter, we also develop an automation flow, together with an accurate performance estimator, to automatically generate the best BitBlender design. Experimental results show that, on the AMD/Xilinx Alveo U280 FPGA, BitBlender achieves a throughput up to 2,194 MQueries/s (i.e., $8.8 \mathrm{~GB} / \mathrm{s}$) for a $\mathrm{9 6 M b}$ bit-vector with 0.01% false-positive rate. It achieves up to 10.4x speedup over a 24-thread CPU implementation and up to 4.9x speedup over a naively-duplicated multi-stream FPGA design. BitBlender will be released soon at https://***/SFU-HiAccel/BitBlender.

关键词： Matched filters Schedules Automation Prevention and mitigation System recovery throughput System-on-chip logic field programmable gate arrays Streams

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HSTL IO Standards Based Low Power Implementation of Elliptic Curve Cryptography (ECC) on FPGA

HSTL IO Standards Based Low Power Implementation of Elliptic...

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Smart Information Systems and Technologies (SIST), IEEE international conference on

作者： Pushpanjali Pandey Ashish Kumar Singh Keshav Kumar Hardik Gohel Leila Rzayeva Bishwajeet Pandey Cyber Security Division Gyancity Research Consultancy Greater Noida India Department of EEE Jain University Bangalore India Department of CSE University of Houston Victoria USA Dept of IS&CS Astana IT University Astana Kazakhstan

ISBN: (数字)9798350374865

ISBN: (纸本)9798350374872

there is a new trend in researcher to use elliptical curve theory for derivation of an efficient, faster and smaller key that will use in lightweight cryptography also known as elliptical curve cryptography (ECC). In this work, we are using High Speed Transceiver logic (HSTL) IO standard to develop an energy efficient ECC and implementing the Hardware Description Language (HDL) code of ECC on Kintex-7 field programmable Gate Array (FPGA). HSTL_II_18 is taking 53.73 % more power in comparison to HSTL_I IO standards. the implementation with HSTL_I or HSTL_II_18 will deliver same result of encryption but power requirement will change. Wise selection of IO standards playing an important role in overall power dissipation during implementation of ECC on FPGA.

关键词： programmable logic arrays logic gates Elliptic curve cryptography Transceivers Power dissipation logic Hardware design languages

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HLS_Profiler: Non-Intrusive Profiling tool for HLS based applications 22

HLS_Profiler: Non-Intrusive Profiling tool for HLS based App...

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13th Annual ACM/SPEC international conference on Performance Engineering (ICPE)

作者： Sumeet, Nupur Deeksha Nambiar, Manoj Tata Consultancy Serv Res Mumbai Maharashtra India

ISBN: (纸本)9781450391597

the High-Level Synthesis (HLS) tools aid in simplified and faster design development without familiarity with Hardware Description Language (HDL) and Register Transfer logic (RTL) design flow that can be implemented on an FPGA (field programmable Gate Array). However, it is not straight forward to trace and link source code to synthesized hardware design. On the other hand, the traditional RTL-based design development flow provides the fine-grained performance profile through waveforms. With the same level of visibility in HLS designs, the designers can identify the performance-bottlenecks and obtain the target performance by iteratively fine-tuning the source code. Although, the HLS development tools provide the low-level waveforms, interpreting them in terms of source code variables is a challenging and tedious task. Addressing this gap, we propose to demonstrate an automated profiler tool, HLS_Profiler, that provides a performance profile of source code in a cycle-accurate manner.

关键词： Hardware profiling HLS Designs Performance Profile Performance Analysis

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Revealing Untapped DSP Optimization Potentials for FPGA-Based Systolic Matrix Engines

Revealing Untapped DSP Optimization Potentials for FPGA-Base...

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international conference on field programmable logic and applications

作者： Jindong Li Tenglong Li Guobin Shen Dongcheng Zhao Qian Zhang Yi Zeng Brain-inspired Cognitive Intelligence Lab Institute of Automation Chinese Academy of Sciences Center for Long-term Artificial Intelligence School of Artificial Intelligence University of Chinese Academy of Sciences School of Future Technology Key Laboratory of Brain Cognition and Brain-inspired Intelligence Technology Chinese Academy of Sciences

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Systolic architectures are widely embraced by neural network accelerators for their superior performance in highly parallelized computation. the DSP48E2s serve as dedicated arithmetic blocks in Xilinx Ultrascale series FPGAs and constitute a fundamental component in FPGA-based systolic matrix engines. Harnessing the full potential of DSP48E2s in architectural design can result in significant performance enhancements for systolic architectures on Ultrascale series FPGAs. this paper unveils several previously untapped DSP optimization techniques capable of further enhancing FPGA-based systolic matrix engines. We apply these techniques to two well-known systolic architectures: Google TPUv1 and Xilinx Vitis AI DPU. With the proposed techniques, our design achieves substantial resource and power reduction compared to the open-source TPUv1 FPGA implementation and the Vitis AI DPU implementation in the same parallelism setting. We also demonstrate the applicability of our techniques to neuromorphic hardware for supporting spiking neural network acceleration.

关键词： Neuromorphics Prefetching Computer architecture Spiking neural networks Hardware Systolic arrays Artificial intelligence field programmable gate arrays Engines Optimization

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FlexiMem: Flexible Shared Virtual Memory for PCIe-attached FPGAs

FlexiMem: Flexible Shared Virtual Memory for PCIe-attached F...

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international conference on field programmable logic and applications

作者： Canberk Sönmez Mohamed Shahawy Cemalettin Cem Belentepe Paolo Ienne École Polytechnique Fédérale de Lausanne Lausanne Switzerland

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Shared Virtual Memory (SVM) is a mechanism that allows host-side applications and FPGA accelerators to access the same virtual address space. It enables accelerating algorithms with unpredictable memory access patterns by making transparent pointer sharing possible. Even for applications with predictable memory access patterns, SVM helps by eliminating manual data movement. FlexiMem is a customizable SVM system that uses FPGA-addressable memory resources to store virtual memory pages, rather than directly accessing the host memory, to achieve high throughput and low latency. On the FPGA side, FlexiMem features a highly-flexible interconnect that, for the first time, allows for configuring address and payload data paths independently for SVM systems. It supports multiple master and slave devices sharing the same address space, such as accelerators issuing many memory requests in parallel to multiple memory banks. With our interconnect design, we provide numerous specialization dimensions to optimize the SVM system for a given workload. For example, irregular applications with short accesses to memory require an address translation for each data transfer. Such applications can take advantage of a highly parallelized address data path and an increased number of TLBs working in parallel. In contrast, regular and bursting applications transfer a small number of address packets per many data packets, and they can tolerate a lightweight address data path with a single translation unit. FlexiMem also provides address translation units with reconfigurable capacities and page sizes to be tailored to the needs of the application. On the host side, FlexiMem leverages the Linux userfaultfd API and vendor-provided IPs and drivers for automatic data movement initiated by software. Blocks of memory allocated by the FlexiMem API can be passed freely to the FPGA or other host-side libraries, without requiring any kind of explicit data movement. We evaluate several experimental setups

关键词： Support vector machines Memory management Manuals throughput Prediction algorithms Software Main-secondary Low latency communication field programmable gate arrays Payloads

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Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits

Fast Switching Activity Estimation for HLS-Produced Dataflow...

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international conference on field programmable logic and applications

作者： Jiantao Liu Maksymilian Graczyk Andrea Guerrieri Lana Josipović Department of Information Technology and Electrical Engineering ETH Zurich Zurich Switzerland EPFL School of Computer and Communication Sciences Lausanne Switzerland HES-SO School of Engineering Sion Switzerland

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

High-level synthesis (HLS) tools generate hardware designs from high-level software languages while sidestepping intricate low-level hardware details. However, HLS tools struggle with precise dynamic power estimation and optimization: the high abstraction level they operate on typically contains no or limited information on low-level circuit details that power consumption depends on. Dataflow circuits have recently been explored in the HLS context; apart from their ability to achieve performance that is superior to standard HLS-generated circuits, their well-defined structure and computational model offer entirely new opportunities for reasoning about power at the HLS level. this paper exploits this insight to present an accurate switching activity estimator for HLS-produced dataflow circuits. Our estimator combines the knowledge about the dataflow circuit structure with software profiling and detailed glitching analysis to estimate the circuit’s switching activity with an average error rate of 1.8% and average speedup of $17.8 \times$ compared with a cycle-accurate simulator. Our technology-agnostic solution makes a critical advancement in HLS power estimation and sets the stage for integrating power optimization within the HLS process.

关键词： Measurement Accuracy Power demand Estimation Hardware Software logic Optimization Standards Switching circuits

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