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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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SoC Scan-Chain Verification Utilizing FPGA-based Emulation Platform and SCE-MI Interface 27

SoC Scan-Chain Verification Utilizing FPGA-based Emulation P...

引用

27th IEEE international System-on-Chip conference (IEEE SOCC)

作者： Tomas, Bill Jason Jiang, Yingtao Yang, Mei Univ Nevada Dept Elect & Comp Engn Las Vegas NV 89154 USA

ISBN: (纸本)9781479933785

Scan-chain is a well-established design-for-testability (DFT) methodology used for testing digital circuits. As SoC complexity increases, thousands of registers can be used in a design, which makes it difficult to implement full-scan testing. More so, as the complexity of the scan algorithm is dependent on the number of design registers, large SoC scan designs can no longer be verified in RTL simulation unless portioned into smaller sub-blocks. this paper proposes a methodology to decrease scan-chain verification time utilizing SCE-MI (Standard for Co-Emulation Modeling Interface protocol) and an FPGA-based emulation platform. A high-level (SystemC) testbench and FPGA synthesizable hardware transactor models are developed for the ISCAS89 S400 benchmark circuit for high-speed communications between the CPU workstation and the FPGA emulator. the emulation results are compared to other verification methodologies, and found to be 82% faster than regular RTL simulation. In addition, the emulation runs in the MHz speed range, allowing the incorporation of software applications, drivers, and operating systems, as opposed to the Hz range in RTL simulation.

关键词： Acceleration Clocks Emulation field programmable gate arrays Hardware Ports (Computers) Software simulating field programmable gate arrays Timing devices Computer hardware acceleration computer software Resistor Transistor logic Scanning Algorithm Registers

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A heterogeneous GASNet implementation for FPGA-accelerated computing 14

A heterogeneous GASNet implementation for FPGA-accelerated c...

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8th international conference on Partitioned Global Address Space Programming Models, PGAS 2014

作者： Willenberg, Ruediger Chow, Paul Dept. of Electrical and Computer Engineering University of Toronto TorontoON Canada

ISBN: (纸本)9781450332477

this paper introduces an effort to incorporate reconfigurable logic (FPGA) components into the Partitioned Global Address Space model. For this purpose, we have implemented a heterogeneous implementation of GASNet that supports distributed applications with software and hardware components and easy migration of kernels from software to hardware. We present a use case and preliminary performance numbers. Copyright 2014 ACM 978-1-4503-3247-7/14/10...$15.00.

关键词： field programmable gate arrays (FPGA)

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Audio De-noising by Spectral Subtraction Technique Implemented on Reconfigurable Hardware 7

Audio De-noising by Spectral Subtraction Technique Implement...

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7th international conference on Contemporary Computing (IC3)

作者： Biswas, Tanmay Pal, Chandrajit Mandal, Sudhindu Bikash Chakrabarti, Amlan Univ Calcutta AK Choudhury Sch Informat Technol Kolkata 700073 W Bengal India

ISBN: (纸本)9781479951734

this paper proposes an efficient hardware architecture for the spectral subtraction algorithm applied to speech enhancement. Spectral subtraction algorithm is widely used in audio de-noising applications. the proposed architecture uses a novel approach to estimate environmental noise from speech adaptively. After estimating the noise from the input speech the noise samples are subtracted, making it noise free. In this design we have two principal blocks, the noise estimation-subtraction block and the phase block, which are executed concurrently exploiting the parallel logic blocks of field programmable gate array (FPGA). We have implemented our design on Spartan6 LX45 FPGA, which also meets the high speed requirements. Resource utilization and delay information for the different blocks in our design are presented. Our proposed hardware implementation shows a better SNR value compared to the original software implementation. To the best of our knowledge, this work is the first of its kind of implementation in regards to FPGA based hardware design for adaptive noise filtering in speech.

关键词： Spectral Subtraction Digital Signal Processing (DSP) field programmable Gate Array (FPGA) System Generator

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Fuzzy logic for omnidirectional mobile platform control based in FPGA and Bluetooth communication 13

Fuzzy logic for omnidirectional mobile platform control base...

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13th Mexican international conference on Artificial Intelligence, MICAI 2014

作者： Peña-Cabrera, Mario Antonio-Gómez, J.M. Osorio, Román Gómez, Humberto Lomas, Victor López-Juárez, Ismael Universidad Nacional Autónoma de México Mexico D.F. Mexico CINVESTAV Saltillo Mexico

ISBN: (纸本)9781479999002

An Omni directional mobile platform control using the intelligence technique of Fuzzy logic is showed in the article, the control allows a practical and reliable driving control of 4 Omni directional wheels, implemented in FPGA allowing to have an independent and autonomous single chip system out of a central computer dependence in order to be used with different applications like service robots platforms. An additional feature is performed by using Bluetooth communication with a cellular phone based on a smartphone OS Android as the handset control device. Driving movement for the mobile platform is limited for 8 directions, a Fuzzy logic module controls the travelling of the platform with independent movement for each wheel, physical feedback is implemented by using electronic decoders. © 2014 IEEE.

关键词： field programmable gate arrays (FPGA)

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Flexible Reconfigurable Architecture for DSP applications 27

Flexible Reconfigurable Architecture for DSP Applications

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27th IEEE international System-on-Chip conference (IEEE SOCC)

作者： Obeid, Abdulfattah M. Qasim, Syed Manzoor BenSaleh, Mohammed S. Marrakchi, Zied Mehrez, Habib Ghariani, Heni Abid, Mohamed KACST Commun & Informat Technol Inst Riyadh Saudi Arabia Univ Pierre & Marie Curie Paris VI LIP6 ASIM Lab Paris France Univ Sfax Natl Engn Sch Sfax CES Lab Sfax Tunisia

ISBN: (纸本)9781479933785

As the flexibility offered by fine-grained field programmable gate array (FPGA) comes at a significant cost of area, speed, and power, there is a trend to use coarse-grained architecture (CGA) for dataflow applications requiring high computational resources. Existing CGA solutions are characterized according to the general organization, the processing element architecture, the basic interconnect structure and their reconfiguration characteristics. Based on the study of several digital signal processing (DSP) applications and their implemented VLSI architectures, we propose a CGA with parameterizable and flexible blocks based on a generic matrix and interconnected by a configurable network. the proposed architecture provides a good tradeoff between flexibility and performance-density. A CAD tool is developed to automate the implementation of the design on the architecture. A synthesizable VHDL code generator is also developed in order to further explore and validate the proposed architecture. the unification of coarse-grained logic block and bus-based interconnection bridges the gap between application-specific integrated circuit (ASIC) and CGA, resulting in area reduction from 40x to 6x, respectively. Experimental results demonstrate the performance and efficiency of the proposed architecture to implement DSP designs.

关键词： Coarse-grained architecture DSP applications flexible FPGA reconflgurable architecture

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Program-based and model-based PLC design environment for multicore FPGA architectures 11

Program-based and model-based PLC design environment for mul...

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11th international conference on Informatics in Control, Automation and Robotics, ICINCO 2014

作者： Economakos, Christoforos Skarpetis, Michael Economakos, George Technological Educational Institution of Sterea Ellada Department of Automation Engineering Psahna EviaGR34400 Greece National Technical University of Athens School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory Heroon Polytechniou 9 Zografou AthensGR15780 Greece

ISBN: (纸本)9789897580390

Digital design has been growing rapidly during the last years, offering advanced implementation solutions for a diversity of appliances and instruments, integrating different sensors and actuators. this has a great impact on embedded automation, where traditional programmable logic Controllers (PLCs) have been gradually replaced by high performance Embedded Controllers, Digital Signal Processor (DSP) chips and, more recently, power efficient field programmable Gate Arrays (FPGAs). Such new implementation platforms bring together efficient design methodologies, like model-based design and high-level or C level program-based design. In their turn, new design methodologies are accompanied by new design technologies like Intellectual Property (IP) based design and High-Level Synthesis (HLS). this paper presents a design environment that utilizes program-based and model-based design, for the development of PLC applications. Specifically, a tool flow is constructed that supports either the design of new control algorithms or the translation of existing algorithms into C. then, HLS and FPGA implementation tools are adopted, to implement the selected algorithms as mul-ticore, embedded designs, offering performance improvements and hardware utilization efficiency. Overall, the proposed methodology and underlying tool flow support a novel high productivity prototyping platform for digital control applications, with very promising future extension capabilities.

关键词： programmable logic controllers

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Design of an academic microcontroller and its application to authenticated encryption

Design of an academic microcontroller and its application to...

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24th international conference on Electronics, Communications and Computers, CONIELECOMP 2014

作者： Juárez Arellano, Alejandro Mancillas López, Cuauhtemoc De La Fraga, Luis Gerardo Cinvestav Computer Science Department Av. IPN 2508 07360 Mexico D.F. Mexico

ISBN: (纸本)9781479934690

In this work we present the design and implementation on FPGAs of a 16 bit microcontroller. Since this microcontroller has academic purposes, its architecture is simple, complete and open. Furthermore, its assembler language was also designed and a translator program in Python is provided. the arithmetic/logic unit designed only include integer operations, and we aggregate a carry free multiplier to make easy some computations needed in cryptographic and coding theory applications which require binary field arithmetic. To demonstrate its functionality we choose a non trivial application, the implementation of two Authenticated Encryption schemes CCM and GCM. Our design can be used in economic range FPGAs as Spartan 3 or faster range as Virtex 5 or higher © 2014 IEEE.

关键词： field programmable gate arrays (FPGA)

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Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation

Hardware in the Loop Simulation Model of BLDC Motor Taking A...

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10th international conference on Mechatronics

作者： Sova, V. Grepl, R. Brno Univ Technol Mechlab Fac Mech Engn Brno 61669 Czech Republic

ISBN: (纸本)9783319022949

this paper presents Hardware in the Loop (HIL) simulation of the BLDC motor used in aerospace applications. Due to a high frequency driving signals and a high dynamics of the electrical part of the BLDC motor, the utilization of FPGA is necessary. the algorithm is distributed between the CPU and the FPGA and targeted to dSPACE modular hardware.

关键词： field programmable gate arrays (FPGA)

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through the eye of the PLC: Semantic security monitoring for industrial processes 14

Through the eye of the PLC: Semantic security monitoring for...

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30th Annual Computer Security applications conference, ACSAC 2014

作者： Had iosmanović, Dina Sommer, Robin Zambon, Emmanuele Hartel, Pieter H. Delft University of Technology Netherlands ICSI/LBNL BerkeleyCA United States University of Twente Security Matters B.V. Netherlands University of Twente Netherlands

ISBN: (纸本)9781450330053

Off-the-shelf intrusion detection systems prove an ill fit for protecting industrial control systems, as they do not take their process semantics into account. Specifically, current systems fail to detect recent process control attacks that manifest as unauthorized changes to the configuration of a plant s programmable logic controllers (PLCs). In this work we present a detector that continuously tracks updates to corresponding process variables to then derive variablespecific prediction models as the basis for assessing future activity. Taking a specification-agnostic approach, we passively monitor plant activity by extracting variable updates from the devices network communication. We evaluate the capabilities of our detection approach with traffic recorded at two operational water treatment plants serving a total of about one million people in two urban areas. We show that the proposed approach can detect direct attacks on process control, and we further explore its potential to identify more sophisticated indirect attacks on field device measurements as well.

关键词： programmable logic controllers

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Pattern-based FPGA logic block and clustering algorithm

Pattern-based FPGA logic block and clustering algorithm

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international conference on field programmable logic and applications

作者： Xifan Tang Pierre-Emmanuel Gaillardon Giovanni De Micheli Ecole Poly technique Fédérale de Lausanne (EPFL) Switzerland

In classical FPGA, LUTs and DFFs are pre-packed into BLEs and then BLEs are grouped into logic blocks. We propose a novel logic block architecture with fast combinational paths between LUTs, called pattern-based logic blocks. A new clustering algorithm is developed to release the potential of pattern-based logic blocks. Experimental results show that the novel architecture and the associated clustering algorithm lead to a 14% performance gain and a 8% wirelength reduction with a 3% area overhead compared to conventional architecture in large control-instensive benchmarks.

关键词： Table lookup field programmable gate arrays Clustering algorithms Routing Standards Bismuth Delays

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