检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,876 篇 会议
30 篇 期刊文献
7 册 图书

馆藏范围

1,913 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,244 篇 工学
- 1,042 篇 计算机科学与技术...
- 729 篇 软件工程
- 407 篇 电气工程
- 183 篇 电子科学与技术（可...
- 74 篇 信息与通信工程
- 63 篇 控制科学与工程
- 33 篇 仪器科学与技术
- 30 篇 机械工程
- 26 篇 动力工程及工程热...
- 23 篇 建筑学
- 17 篇 土木工程
- 15 篇 核科学与技术
- 13 篇 光学工程
- 13 篇 生物工程
- 10 篇 材料科学与工程（可...
- 10 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
171 篇 理学
- 101 篇 数学
- 45 篇 物理学
- 18 篇 生物学
- 17 篇 系统科学
- 9 篇 统计学（可授理学、...
- 6 篇 化学
49 篇 管理学
- 38 篇 管理科学与工程(可...
- 19 篇 工商管理
- 14 篇 图书情报与档案管...
16 篇 医学
- 14 篇 临床医学
- 12 篇 特种医学
14 篇 法学
- 12 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
5 篇 农学
5 篇 军事学
2 篇 教育学

主题

834 篇 field programmab...
688 篇 field programmab...
276 篇 hardware
157 篇 computer archite...
126 篇 logic gates
112 篇 table lookup
87 篇 throughput
87 篇 clocks
83 篇 random access me...
79 篇 routing
74 篇 software
72 篇 acceleration
66 篇 delays
65 篇 optimization
62 篇 kernel
54 篇 registers
54 篇 logic
50 篇 switches
49 篇 algorithm design...
47 篇 system-on-chip

机构

14 篇 univ toronto dep...
9 篇 imperial coll lo...
8 篇 school of comput...
8 篇 department of co...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 brigham young un...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 inesc-id univers...
5 篇 swiss fed inst t...
5 篇 department of el...

作者

31 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 koch dirk
14 篇 wayne luk
12 篇 wilton steven j....
12 篇 ienne paolo
11 篇 betz vaughn
10 篇 fahmy suhaib a.
10 篇 cheung peter y. ...
9 篇 vaughn betz
9 篇 constantinides g...
9 篇 prasanna viktor ...
9 篇 amano hideharu
8 篇 paolo ienne
8 篇 chow paul
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 teich juergen
7 篇 suhaib a. fahmy
7 篇 alonso gustavo

语言

1,885 篇 英文
24 篇 其他
4 篇 中文

检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

共 1913 条记录，以下是951-960 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Mixed-architecture process scheduling on tightly coupled reconfigurable computers

Mixed-architecture process scheduling on tightly coupled rec...

引用

international conference on field programmable logic and applications

作者： Brandon Kyle Hamilton Michael Inggs Hayden Kwok-Hay So Department of Electical Engineering University of Cape Town Cape Town South Africa Department of Electrical & Electronic Engineering University of Hong Kong Hong Kong

the design and implementation of a multitasking runtime system for mixed-architecture applications on a tightly coupled FPGA-CPU platform is presented. the runtime environment and the user applications assume an underlying machine that encompasses multiple computing architectures within a unified machine model. Using this model, a unified process scheduling mechanism was developed that enables concurrent execution of multiple mixed-architecture processes. Scheduling and allocation strategies, including blocking and preemption, were implemented and evaluated with respect to performance and fairness on a Xilinx Zynq platform using a mix of synthetic workloads.

关键词： Computer architecture Runtime field programmable gate arrays Hardware Context Switches Processor scheduling

来源：评论

学校读者我要写书评

暂无评论

Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoC

Function-Level Processor (FLP): Raising Efficiency by Operat...

引用

IEEE 25th international conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Tabkhi, Hamed Bushey, Robert Schirner, Gunar Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA Analog Devices Inc ADI Embedded Syst Prod & Technol Norwood MA USA

ISBN: (纸本)9781479936090

the exponential growth in computation demand drives chip vendors to heterogeneous architectures combining Instruction-Level Processors (ILPs) and custom HW Accelerators (HWACCs) in an attempt to provide the needed processing capabilities while meeting power/energy requirements. ILPs, on one hand, are highly flexible, but power inefficient. Custom HWACCs, on the other hand, are inflexible (focusing on dedicated kernels), but highly power efficient. Since, designing HWACCs for every application is cost prohibitive, large portions of applications still run inefficiently on ILPs. New processing architectures are needed that combine the power efficiency of HWACCs while still retaining sufficient flexibility to realize applications across targeted market segments. this paper introduces Function-Level Processors (FLPs) to fill the gap between ILPs and dedicated HWACCs. FLPs are comprised of configurable Function Blocks (FBs) implementing selected functions which are then interconnected via programmable point-to-point connections constructing an extensible/configurable macro data-path. An FLP raises programming abstraction to a Function-Set Architecture (FSA) controlling FBs allocation, configuration and scheduling. We demonstrate FLP benefits with an industry example of the Pipeline-Vision Processor (PVP). We highlight the gained flexibility by mapping 10 embedded vision applications entirely to the FLP-PVP offering up to 22.4 GOPs/s with average power of 120 mW. the results also demonstrate that our FLP-PVP solution consumes 14x-18x less power than an ILP and 5x less power than a hybrid ILP+ HWACCs solution.

关键词： fault-location problem PROCESSOR inductive logic programming dynamic efficiency Exponential Growth average power ARCHITECTURE Power (Psychology) Energy sources macro data Target marketing Connection points

来源：评论

学校读者我要写书评

暂无评论

Portable module relocation and bitstream compression for Xilinx FPGAs

Portable module relocation and bitstream compression for Xil...

引用

international conference on field programmable logic and applications

作者： Christian Beckhoff Dirk Koch Jim Torresen University of Oslo Norway

this paper presents a novel methodology for generating and compressing configuration bitstreams for modules that can be executed at different positions of an FPGA. the presented methodology for bitstream generation and compression does not need deep knowledge of the bitstream format and it is independent of the target (Xilinx) FPGA family. the approach consists of a design phase where partial bitstreams are decomposed into sequences of module dependent and module independent pieces of configuration data. At run-time, this data can then be recomposed for the individual placement positions by a special DMA configuration controller as one atomic operation without any further software interaction. Our experiments demonstrate that module relocation and fast partial reconfiguration can be implemented at low logic cost.

关键词： field programmable gate arrays Clocks Digital signal processing Routing Compression algorithms Hardware Encoding

来源：评论

学校读者我要写书评

暂无评论

Asynchronously assisted FPGA for variability

Asynchronously assisted FPGA for variability

引用

international conference on field programmable logic and applications

作者： Hock S. Low Delong Shang Fei Xia Alex Yakovlev Systems Design Group Newcastle University Newcastle upon Tyne UK

the effect of variability has become increasingly significant as a result of technology geometry scaling. this paper describes Asynchronous Assisting logic (AAL) blocks and the method of introducing them into modern FPGA architecture, in order to increase tolerance of the wide range latency variations caused by parametric variation, and temperature and supply voltage fluctuations. the proposed method leverages the availability of variation maps and suggests deploying configurable AAL blocks only into the variation critical paths - reinforcing rather rerouting/remapping. this method reduces the size overhead significantly which normally will be incurred by fully asynchronous designs. the proposed technique maintains the existing FPGA architecture allowing potential reuse of design flow. Simulations show correct functionality given regularly variable, randomly variable and capacitor switching energy harvester voltage supplies.

关键词： field programmable gate arrays Switches Silicon Clocks logic gates

来源：评论

学校读者我要写书评

暂无评论

A combination of multi-edge coding and independent coding lines for time-to-digital conversion

A combination of multi-edge coding and independent coding li...

引用

international conference on field programmable logic and applications

作者： Dominik Sondej Ryszard Szplet Military University of Technology Warsaw Poland

the paper describes a new method for time-to-digital conversion that allows achieving the conversion resolution far below the propagation time of the fastest delay buffer in integrated circuit (IC). the method is a combination of the multi-edge time coding and time digitization in independent coding lines. the implementation of such combination and assessment of its effectiveness are the main aims of this research. the article also describes the main design issues that were solved during the implementation of method in an FPGA device. they include: the generation of a pattern square signal with a certain amount of edges and possibly minimal delays between them, the elimination of bubble errors and reduction of internal interferences in IC.

关键词： Encoding field programmable gate arrays Delays Delay lines Signal resolution

来源：评论

学校读者我要写书评

暂无评论

Multi-directional error correction schemes for SRAM-based FPGAs

Multi-directional error correction schemes for SRAM-based FP...

引用

international conference on field programmable logic and applications

作者： Shyamsundar Venkataraman Rui Santos Sidharth Maheshwari Akash Kumar Department of Electrical & Computer Engineering National University of Singapore

Readback scrubbing is considered as an effective mechanism to correct errors in Static-RAM (SRAM)-based field programmable Gate Arrays (FPGAs). However, current solutions have a low error correction percentage per unit area overhead. this paper proposes two new error detection/correction mechanisms that combine frame readback scrubbing with error correction codes (ECCs) that are applied in multiple directions, to achieve a high error correction percentage per unit area overhead. Experiments conducted show that the proposed schemes have an excellent error correction percentage (over 99%), especially for multi-bit upsets, while using up to 59.37% lesser area overhead compared with other state-of-the-art.

关键词： field programmable gate arrays Error correction Error correction codes Computer architecture Hardware Circuit faults Equations

来源：评论

学校读者我要写书评

暂无评论

Ready PCIe data streaming solutions for FPGAs

Ready PCIe data streaming solutions for FPGAs

引用

international conference on field programmable logic and applications

作者： thomas B. Preußer Rainer G. Spallek Technische Universitat Dresden Dresden Sachsen DE Technische Universität Dresden Germany

the PCIe attachment of FPGA accelerators within host workstations is convenient and offers a high-performance direct integration. FPGA-boards designed and equipped as PCIe extension cards are available off-the-shelf. this paper gives an overview on options to provide data streaming abstractions in user applications using PCIe technology. RIFFA and Xillybus are straightforward implementations, which aim at providing ready solutions at this level. this paper will describe these platforms and evaluate them in terms of their ease of use, their perceived maturity and the performance metrics bandwidth and latency. It concludes with providing a brief guideline on how to select the proper platform depending on the usage context.

关键词： field programmable gate arrays throughput Bandwidth Libraries Linux Standards Performance evaluation

来源：评论

学校读者我要写书评

暂无评论

RAM-based hardware accelerator for network data anonymization

RAM-based hardware accelerator for network data anonymizatio...

引用

international conference on field programmable logic and applications

作者： Fumito Yamaguchi Kanae Matsui Hiroaki Nishi Graduate School of Science and Technology Keio University Yokohama Japan

Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization has been discussed. there have been many studies of anonymization techniques and their implementation in software applications. However, limited research has been undertaken regarding hardware-based anonymizers. this paper proposes and evaluates a RAM-based anonymization architecture that maintains both high throughput and a low information-loss ratio.

关键词： Hardware Random access memory throughput Software field programmable gate arrays Table lookup

来源：评论

学校读者我要写书评

暂无评论

Methods for implementation of feedback loops in high speed FPGA applications

Methods for implementation of feedback loops in high speed F...

引用

international conference on field programmable logic and applications

作者： Nima Safari Volker Mauer Shahin Gheitanchi Wireless SSE Altera Corporation High Wycombe UK

In many Digital Signal Processing (DSP) modules, increasing the number of pipelining stages to achieve higher throughput may break the module functionality if a feedback-loop exists in the algorithm. this paper addresses a novel algorithmic-level technique to modify implementation of feedback loops to allow deeper pipelining while sustaining the module functionality. An equivalent model for a first-order Infinite Impulse Response (IIR) filter can be obtained by a cascade model including a higher order repeated-pole IIR filter followed by a Finite Impulse Response (FIR) filter. the order of the repeated-pole IIR filters, and hence the number of pipelining stages can be chosen to meet the Fmax requirements. the model is further developed to include a class of mathematical recursive functions to cover many different DSP applications.

关键词： IIR filters Pipeline processing Feedback loop Digital signal processing Registers Finite impulse response filters field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Area implications of memory partitioning for high-level synthesis on FPGAs

Area implications of memory partitioning for high-level synt...

引用

international conference on field programmable logic and applications

作者： Luca Gallo Alessandro Cilardo David thomas Samuel Bayliss George A. Constantinides University of Naples Federico II Napoli Imperial College London London U.K

FPGAs normally have numerous independent memory banks that can be accessed simultaneously, potentially offering a very large memory bandwidth. Adopting a suitable application-based memory partitioning strategy is thus vital to take full advantage of the memory architecture. In addition to improving the potential memory bandwidth, partitioning also affects the area complexity of the generated system because the required steering logic depends on the partitioning scheme. this work describes the area implications of a lattice-based memory partitioning technique in the context of high-level synthesis for FPGAs. Experimental results with a commercial HLS tool show that the proposed partitioning technique improves area efficiency compared to alternative approaches.

关键词： Lattices Switches Memory management field programmable gate arrays Table lookup Schedules Parallel processing

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共192页 << < 92 93 94 95 96 97 98 99 100 101 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：