To get maximum energy efficiency from adiabatic logic circuits several charge-recovery power clock generators (PCGs) have been published in recent years. this paper compares and analyzes the performance and energy eff...
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ISBN:
(纸本)0769522645
To get maximum energy efficiency from adiabatic logic circuits several charge-recovery power clock generators (PCGs) have been published in recent years. this paper compares and analyzes the performance and energy efficiency of various PCGs in a uniform test environment. the test benches are layed out in a standard 0.18 mum CMOS technology and the results are mainly based on post layout simulations.
We present an overview on the AT(x) approach which is capable of automatically analyzing programs with respect to given tests and a reference solution. In the context of small homework assignments with precisely descr...
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ISBN:
(纸本)3540255605
We present an overview on the AT(x) approach which is capable of automatically analyzing programs with respect to given tests and a reference solution. In the context of small homework assignments with precisely describable tasks, AT(P), a Prolog instance of the general AT(x) framework, is able to find many of the errors usually made by students and to communicate them in a manner understandable for beginners in Prolog programming. the system is being used in distance education where direct communication between students and tutors is most of the time not possible.
In this paper a CMOS logic delay optimization algorithm was used to find the optimal number of pass transistors to use for buffer insertion into a CPL chain. the result was then used as a guide during the design of a ...
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ISBN:
(纸本)0769522645
In this paper a CMOS logic delay optimization algorithm was used to find the optimal number of pass transistors to use for buffer insertion into a CPL chain. the result was then used as a guide during the design of a 64-bit high-speed static adder Simulation results indicated a worst-case critical-path delay of 656ps for a device based on TSMC 0.18 mum technology.
this paper presents a technology mapper for combinational circuits targeting Actel's SX-A/AX logic module. To the best of our knowledge, this is the first such effort reported in the literature. It exploits the mo...
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ISBN:
(纸本)0769522645
this paper presents a technology mapper for combinational circuits targeting Actel's SX-A/AX logic module. To the best of our knowledge, this is the first such effort reported in the literature. It exploits the module architecture completely to come up with good mapping solutions. In the absence of similar works, results have been compared with act1 and act2 mappers and found to be encouraging.
A conventional approach to the simulation of crosstalk-induced delay faults is commonly centered around an electrical-level circuit simulation. While yielding high accuracy, the process is time-consuming and may no lo...
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ISBN:
(纸本)0769522645
A conventional approach to the simulation of crosstalk-induced delay faults is commonly centered around an electrical-level circuit simulation. While yielding high accuracy, the process is time-consuming and may no longer be feasible for modem, high-density VLSI circuits. To address this issue, we propose and develop a novel approach for gate-level simulation of crosstalk delay faults caused by coupling between aggressor and victim signal lines. Our algorithm extends existing fundamental principles of logic event-driven simulation to crosstalk delay faults excitation, injection, and verification. In addition, the simulator is capable of handling multiple-aggressors/single-victim faults in an efficient manner.
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present an approximation model for current in ...
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ISBN:
(纸本)0769522645
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present an approximation model for current in a current comparator circuit. Power reduction is achieved through turning off the redundant comparator circuits using a switch-architecture. Simulations are carried-out for current-mode flash ADC designs and literal generating circuits for MVL. We show that the simple switch architecture with minimum area overhead can be used to trade-off power dissipation with delay in these designs.
this paper proposes a new CLB architecture for FPGAs and an associated testing technique that detects routing errors caused by SEUs in the SRAM configuration memory of the FPGA. the proposed testing technique detects ...
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ISBN:
(纸本)0769522645
this paper proposes a new CLB architecture for FPGAs and an associated testing technique that detects routing errors caused by SEUs in the SRAM configuration memory of the FPGA. the proposed testing technique detects all possible routing errors including bridging faults, and requires a single configuration of only the LUTs of the FPGA. Any routing error that affects the logic of the circuit is detected by the proposed technique in a maximum of 8 clock cycles. It Is noteworthy that the time required for error detection is independent of boththe number of switch matrices and the number of logic blocks in the FPGA.
Recent progress of VR (Virtual Reality) technologies makes it possible to realize the VR space that is synchronized withthe real space. We can hereby build virtual workspace through which a worker in real workspace c...
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ISBN:
(纸本)3540255605
Recent progress of VR (Virtual Reality) technologies makes it possible to realize the VR space that is synchronized withthe real space. We can hereby build virtual workspace through which a worker in real workspace can automatically acquire and invoke appropriate plant maintenance agents. We propose spatial programming which is a manner of VR programming technique, locating various place-dependent agents and web information in VR space, and also describe the interface between agent world and real workspace as an application of spatial programming, towards ubiquitous maintenance.
this paper presents a new fuzzy logic based approach for forecasting the possible path, an agent would follow for reaching a target using sub-goal method. Each agent plans collision-free motion and undertake paths for...
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