We shall present a simple but useful method which detects all multiple stuck-at faults in the application and configuration inputs of LUTs. A novel method for testing of stuck-at faults at control bits of flip flops h...
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ISBN:
(纸本)0769522645
We shall present a simple but useful method which detects all multiple stuck-at faults in the application and configuration inputs of LUTs. A novel method for testing of stuck-at faults at control bits of flip flops has also been proposed. the aim is to integrate testing of LUTs, flip flops and multiplexers which will reduce the number of configurations and hence minimize the testing time.
As we move into the system-on-chip era, test cost is becoming a significant portion of the total cost. Similarly, test synthesis, test pattern generation, pattern compression and pattern validation are consuming signi...
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ISBN:
(纸本)0769522645
As we move into the system-on-chip era, test cost is becoming a significant portion of the total cost. Similarly, test synthesis, test pattern generation, pattern compression and pattern validation are consuming significant portion of the design cycle time. the volume of test generation and validation is high due to the size of the designs as well as the types of tests that are required to be run - scan test patterns for stuck-at and delay tests, logic and memory BIST patterns, IDDQ tests, burn-in tests, and several miscellaneous tests. Designs cannot be taped out without validated test patterns. At the same time, since design timing closure takes up a significant portion of the project time and the timing information is not available until late in the schedule, there is immense pressure on the DFT team to generate and validated patterns in a small time frame. this paper describes a framework for design-for-test which exploits both hierarchy and the inherent parallelism in the DFT jobs to run the jobs in a distributed computing environment so as to minimize the runtime impact.
Withthe growing popularity of parallel computation, researchers are looking for various means to reduce the problem solving time by performing the computations in parallel. While benefiting from parallel computation,...
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the opportunities for additional profit depend very much on the existing plant and energy system. Methanol plant was optimized using mathematical nonlinear programming (NLP) model by including an additional flow rate ...
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ISBN:
(纸本)8251920418
the opportunities for additional profit depend very much on the existing plant and energy system. Methanol plant was optimized using mathematical nonlinear programming (NLP) model by including an additional flow rate of hydrogen (H2) in crude methanol recycle and increasing the methanol production by 2,5 %. the electricity can be generated in methanol recycle using gas turbine. the total additional profit is 2,5 MEUR/a.
We are interested in programming languages for cognitive agents with preferences. We define rule-based agent theories and inference procedures in defeasible logic, and in this setting we discuss patterns of agent beha...
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ISBN:
(纸本)3540304622
We are interested in programming languages for cognitive agents with preferences. We define rule-based agent theories and inference procedures in defeasible logic, and in this setting we discuss patterns of agent behavior called agent types.
Reversibility is of interest in the design of very low-power circuits;it is essential for quantum computation. this paper examines the testability of an important subclass of reversible logic circuits that are compose...
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ISBN:
(纸本)0769522645
Reversibility is of interest in the design of very low-power circuits;it is essential for quantum computation. this paper examines the testability of an important subclass of reversible logic circuits that are composed of k-wire controlled NOT (k-CNOT) gates. Most commonly used stuck-at-fault model (both single stuck-at-fault (i.e. SSF) and multiple stuck-at fault (i.e. MSF)) has been assumed to be type of fault for such circuits. We define a universal test set (UTS) for a family C(n) of n-input circuits with respect to fault model F as a family of test sets T-UTS such that each Qn) has a unique test set T(n) in T-UTS that detects all F-type faults in every member of C(n). We show that if k greater than or equal to 2 for all gates, then the n-wire reversible circuits have a UTS of size n with respect to MSFs. By synthesizing 0-CNOT (inverters) and 1-CNOT gates from 2-CNOT (Toffoli) gates this result can be extended to all circuits of interest. We also present a method for modifying an n-wire reversible circuit to reduce its UTS size to 3. By modeling a k-CNOT gate as a k-input AND gate and a 2-input EXOR gate we then examine testability for the SSF model. Noting their resemblance to classical (irreversible) Reed-Muller circuits, which are well known to be easily testable, we prove that the n-wire reversible circuits have a UTS of size n(2) + 2n + 2. Finally, we turn to the reversible counterparts of another easily-testable classical circuit family, iterative logic arrays (ILAs). We define d-dimensional reversible ILAs (RILAs) and prove that they require a constant number test vectors irrespective of array length under the single cell fault (i.e. SCF) model;this number is determined by the size of the RILA cell's state table.
the proceedings contain 156 papers from Proceedings of the 18thinternationalconference on VLSI Design. the topics discussed include: power-aware, reliable microprocessor design;SoC design methodology: a practical ap...
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the proceedings contain 156 papers from Proceedings of the 18thinternationalconference on VLSI Design. the topics discussed include: power-aware, reliable microprocessor design;SoC design methodology: a practical approach;tuple detection for path delay faults: a method for improving test set quality;variance reduction in Monte Carlo capacitance extraction;accurate stacking effect macro-modeling of leakage power in sub-100nm circuits;lazy constraints and SAT heuristics for proof-based abstraction;synthesis of majority and minority networks and its application to QCA, TPL and SET based nanotechnologies;optimization of mixed logic circuits with application to a 64-bit static adder;and a 160MSPS 8-bit pipeline based ADC.
Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new "oring" node structure to represent partial imp...
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ISBN:
(纸本)0769522645
Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new "oring" node structure to represent partial implications in a graph. the oring node is the contrapositive of the previously used "anding" node. An n-input gate requires one oring and one anding nodes to represent all partial implications. this implication graph is shown to be more complete and more compact compared to the previously published (n+1) anding node graph. Introduction of the new oring node finds more redundancies using the transitive closure method. the second contribution of the present work is a set of new algorithms to update transitive closure for every newly added edge in the implication graph associated with anding and oring nodes. For the ISCAS'85 benchmark circuit c1908, the new graph identifies 5 out of a total of 7 redundant faults. the best known previous implication graph procedure could only identify 2 redundant faults. We analyze the unidentified redundant faults and suggest a possible improvement.
Distributing pieces of knowledge in large, usually distributed organizations is a central problem in Knowledge and Organization Management. Policies for distributing knowledge and information are very often incomplete...
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the hybrid logic H(@) is obtained by adding nominals and the satisfaction operator @ to the basic modal logic. the resulting logic gains expressive power without increasing the complexity of the satisfiability problem...
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ISBN:
(纸本)3540252363
the hybrid logic H(@) is obtained by adding nominals and the satisfaction operator @ to the basic modal logic. the resulting logic gains expressive power without increasing the complexity of the satisfiability problem, which remains within PSpace. A resolution calculus for H(@) was introduced in [5], but it did not provide strategies for ordered resolution and selection functions. Additionally, the problem of termination was left open. In this paper we address both issues. We first define proper notions of admissible orderings and selection functions and prove the refutational completeness of the obtained ordered resolution calculus using a standard "candidate model" construction [10]. Next, we refine some of the nominal-handling rules and show that the resulting calculus is sound, complete and can only generate a finite number of clauses, establishing termination. Finally, the theoretical results were tested empirically by implementing the new strategies into HyLoRes [6,18], an experimental prototype for the original calculus described in [5]. Both versions of the prover were compared and we discuss some preliminary results.
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