In this paper, a CMOS logic delay optimization algorithm was used to find the optimal number of pass transistors to use for buffer insertion into a CPL chain. the result was then used as a guide during the design of a...
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ISBN:
(纸本)0769522645
In this paper, a CMOS logic delay optimization algorithm was used to find the optimal number of pass transistors to use for buffer insertion into a CPL chain. the result was then used as a guide during the design of a 64-bit high-speed static adder. Simulation results indicated a worst-case critical-path delay of 650 ps for a device based on TSMC 0.18 /spl mu/m technology.
this paper presents a technology mapper for combinational circuits targeting ActeVs SX-A/AX logic module. To the best of our knowledge, this is the first such effort reported in the literature. It exploits the module ...
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this paper presents a technology mapper for combinational circuits targeting ActeVs SX-A/AX logic module. To the best of our knowledge, this is the first such effort reported in the literature. It exploits the module architecture completely to come up with good mapping solutions. In the absence of similar works, results have been compared with actl and act2 mappers and found to be encouraging.
this work presents an efficient test solution for VLSI circuits. the test structure is designed with GF(2/sup P/) CA. the introduction to an innovative scheme of logic folding optimizes the cost of test logicthat can...
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this work presents an efficient test solution for VLSI circuits. the test structure is designed with GF(2/sup P/) CA. the introduction to an innovative scheme of logic folding optimizes the cost of test logicthat can not be feasible withthe flattened structure of GF(2) CA/LFSR.
this paper describes how to properly use the object-oriented features of SystemVerilog to model transactions and transactors that execute them. Designers, used to a procedural programming model, will learn how to appr...
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this paper describes how to properly use the object-oriented features of SystemVerilog to model transactions and transactors that execute them. Designers, used to a procedural programming model, will learn how to approach a transactor modeling problem using the object-oriented approach. Software engineers, used to a traditional object-oriented programming model, will learn how to adapt their methods to the special requirements of constrained-random verification. this paper will present clear and concise guidelines that can be followed to create effective, easy-to-use and reusable transactor models. Summary: Transactors ? also known as bus-functional models ? have traditionally been modeled using a procedural interface (API). Commands were provided to use every feature available in the transactor. Several commands were often necessary to configure the transactor or to execute the simplest transaction. If the transactor did not provide a feature required by a particular device under test (DUT) or testcase, it had to be modified or rewritten. By using an object-oriented approach for configuration and interfacing, transactors can easily be used out-of-the-box. A few lines are all that is necessary to create valid random stimulus to a DUT or report observed response to a scoreboard. the use of callback methods eliminates the need for a complex and ever-evolving API. Instead of creating yet-another programming language, it leverages the power of SystemVerilog to extend the functionality of a transactor in ways the original author may not have conceived. Without modification, a ransactor can thus be used and reused effectively. Transactors can also be modeled in an extensible fashion. Extensible transactors allow users to define entirely new transactions and commands, should the ones provided by the original implementation prove insufficient. Usability and reusability of transactors does not happen by accident. With careful design and consistent use model, transactors can
In this paper, we present a methodology for efficient majority/minority network synthesis of arbitrary multioutput Boolean functions. Many emerging nanoscale technologies, such as quantum cellular automata (QCA), tunn...
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ISBN:
(纸本)0769522645
In this paper, we present a methodology for efficient majority/minority network synthesis of arbitrary multioutput Boolean functions. Many emerging nanoscale technologies, such as quantum cellular automata (QCA), tunneling phase logic (TPL), and single electron tunneling (SET), are capable of implementing majority or minority logic very efficiently. However, there exists no comprehensive methodology or design automation tool for general multilevel majority/minority network synthesis. We have built the first such tool, majority logic synthesizer (MALS), on top of an existing Boolean logic synthesis tool. We have performed experiments with 40 MCNC benchmarks. they indicate that up to 68.0% reduction in gate count is possible when utilizing majority logic, withthe average reduction being 21.9%, compared to traditional logic synthesis, in which two-input AND/OR gates in the circuit are converted to majority gates.
One of the emerging challenges in formal property verification (FPV) technology is the problem of deciding whether sufficient properties have been written to cover the design intent. Existing literature on FPV coverag...
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In this paper, we have proposed a design technique for the reversible circuit of binary coded decimal (BCD) adder. the proposed circuit has the ability to add two 4-bits binary variables and it transforms the addition...
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In this paper, we have proposed a design technique for the reversible circuit of binary coded decimal (BCD) adder. the proposed circuit has the ability to add two 4-bits binary variables and it transforms the addition into the appropriate BCD number with efficient error correcting modules where the operations are reversible. We also show that the proposed design technique generates the reversible BCD adder circuit with minimum number of gates as well as the minimum number of garbage outputs.
this paper introduces the implementation of asynchronous pipelined circuits in MOS current-mode logic (MCML). C-element and double-edge-triggered flip-flop are implemented in MCML and used in so-called micropipeline c...
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ISBN:
(纸本)0769522645
this paper introduces the implementation of asynchronous pipelined circuits in MOS current-mode logic (MCML). C-element and double-edge-triggered flip-flop are implemented in MCML and used in so-called micropipeline circuits. the effects of different layout techniques on the performance and power dissipation of an MCML FIFO are also investigated. Based on post-layout simulation results, an asynchronous MCML four-stage FIFO implemented in a standard 0.18 /spl mu/m CMOS technology demonstrates a throughput of 4 GHz while dissipating 3.7 mW. the MCML micropipeline C-element dissipates up to four times less power compared to its conventional static CMOS counterpart at the same throughput of 1.9 GHz.
We propose a novel single event fault/error model based on logic induced fault encoded directed acyclic graph (LIFE-DAG) structured probabilistic Bayesian networks, capturing all spatial dependencies induced by the ci...
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We propose a novel single event fault/error model based on logic induced fault encoded directed acyclic graph (LIFE-DAG) structured probabilistic Bayesian networks, capturing all spatial dependencies induced by the circuit logic. the detection probabilities also act as a measure of soft error susceptibility (an increased threat in nanodomain logic block) that depends on the structural correlations of the internal nodes and also on input patterns. Based on this model, we show that we are able to estimate detection probabilities of single-event faults/errors on IS-CAS'85 benchmarks with high accuracy (zero-error), linear space requirement complexity, and with an order of magnitude (/spl ap/5 times) reduction in estimation time over corresponding BDD based approaches.
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