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international conference on VLSI Design

作者： M. Phadoongsidhi K.K. Saluja Department of Electrical Engineering King Mongkut's Institute of Technology North Bangkok Thailand Department of Electrical and Computer Engineering University of Wisconsin Madison USA

A conventional approach to the simulation of crosstalk-induced delay faults is commonly centered around an electrical-level circuit simulation. While yielding high accuracy, the process is time-consuming and may no longer be feasible for modern, high-density VLSI circuits. To address this issue, we propose and develop a novel approach for gate-level simulation of crosstalk delay faults caused by coupling between aggressor and victim signal lines. Our algorithm extends existing fundamental principles of logic event-driven simulation to crosstalk delay faults excitation, injection, and verification. In addition, the simulator is capable of handling multiple-aggressors/single-victim faults in an efficient manner.

关键词： Sequential circuits Crosstalk Delay Circuit faults Circuit simulation Circuit testing Discrete event simulation Very large scale integration Coupling circuits Computational modeling

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VLSI design challenges for gigascale integration

VLSI design challenges for gigascale integration

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international conference on VLSI Design

作者： S. Borkar VLSI Design Challenges for Gigascale Integration

VLSI system performance increased by five orders of magnitude in the last three decades, made possible by continued technology scaling, improving transistor performance to increase frequency, increasing integration capacity to realize complex architectures, and reducing energy consumed per logic operation to keep power dissipation within limit. the technology treadmill will continue, providing integration capacity of billions of transistors; however, power and energy consumption will be the barriers. Performance at any cost will not be an option in the future; VLSI systems will have to emphasize performance delivered in a given power envelope, with complexity limited by energy efficiency. this paper discusses potential solutions in process technology, circuits, and microarchitectures to exploit future gigascale integration capacity. the system on a chip (SOC) concept will help integrate diverse functional blocks, providing valued performance. the paper concludes with recommendations to the VLSI system designers on how to exploit these emerging paradigms.

关键词： Very large scale integration System performance Frequency logic Power dissipation Energy consumption Costs Energy efficiency Circuits Microarchitecture

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Distributed simulation modeling for manufacturing systems design using XML

Distributed simulation modeling for manufacturing systems de...

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IEEE international conference on Systems Engineering

作者： R. Srinon S. Ramakrishnan Engineering Management and Systems Engineering University of Missouri Rolla Rolla MO USA

Discrete event simulations have been used to model manufacturing systems. Various decomposition methods such as distributed simulations have been employed for this modeling. In the context of distributed simulations, each federate must be able to share the embedded logic with the other federates, irrespective of the software used to design and build such systems. this paper provides an eXtensible Markup Language (XML)-based representation for distributed models that can be shared across the federation of simulations. Specifically, the paper outlines three different model components that forms the basis of a design framework for distributed simulation models - object model (for simulation constructs), logic model (represents information flow within a model and its interactions) and the connectivity model (represents the links among the simulation constructs).

关键词： Manufacturing systems XML Object oriented modeling logic design Automatic control Discrete event simulation Distributed control Systems engineering and theory Context modeling Embedded software

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Preventing deadlock with dynamic message scheduling

Preventing deadlock with dynamic message scheduling

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IEEE international conference on Systems Engineering

作者： E. Gomez Y. Karant K. Schubert Department of Computer Science California State University San Bernardino USA

Although deadlock is not completely avoidable in distributed and parallel programming, we here describe theory and practice of a system that allows us to limit deadlock to situations in which there are true circular data dependences or failure of processes that compute data needed at other processes. this allows us to guarantee absence of deadlock in SPMD computations absent process failure. Our system guarantees optimal ordering of communication statements. We gratefully acknowledge the support of the US National Science Foundation under Award CISE EIA 9810708 without which this work would not have been possible.

关键词： System recovery Dynamic scheduling Message passing Data analysis Processor scheduling Computer science Parallel programming Concurrent computing Distributed computing Databases

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Ambivalent social networks and their consequences for participation

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international JOURNAL OF PUBLIC OPINION RESEARCH 2005年第4期17卷 422-442页

作者： Nir, L Hebrew Univ Jerusalem Dept Commun IL-91905 Jerusalem Israel Hebrew Univ Jerusalem Dept Polit Sci IL-91905 Jerusalem Israel

Does perceived disagreement in political discussion help or hinder citizens' political participation? Some argue that disagreement prompts reflection, perspective-taking, and tolerance. Challengers argue that disagreement fosters ambivalence and hinders participatory activities and turnout. One seminal study that tackled this dilemma formulated the 'cross-pressures' hypothesis (Lazarsfeld, Berelson, & Gaudet, 1944/1968), which posited that the more individuals are betwixt and between conflicting social positions, the longer the time for their vote intention to crystallize (and the lower the likelihood they would vote). this paper offers a critique and refinement of the cross-pressures hypothesis. First, previous studies confounded intra-individual and structural sources of cross-pressures. Second, past operationalizations of exposure to disagreement focused on the sheer amount of opposition to the individual's point of view, rather than his or her exposure to two conflicting points of view. A new measure-network ambivalence-is proposed to capture the latter dynamic. Conceptual and methodological refinements of the cross-pressures hypothesis are tested on a representative sample of voting-age respondents in the United States, interviewed on the American National Election Study 2000 panel (N=1,555). Results suggest that not only were these pressures hardly detrimental to participation, but they also facilitated the formation of considered electoral preferences.

关键词： POLITICAL participation AMBIVALENCE REASONING (logic) NOMINATIONS for office SOCIAL participation

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A new risk management approach deployed over a client/server distributed functional architecture

A new risk management approach deployed over a client/server...

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IEEE international conference on Systems Engineering

作者： V.M. Gulfas C. Abalde L.M. Castro C. Varela Dept. of Comput. Sci. A Coruna Univ. Spain LFCIA - MADS Group. Computer Science Department University of A Coruña Spain

this paper shows our experience in the development of a large, scalable and reliable client/server risk management information system. It was developed using the distributed functional language Erlang for describing the domain logic and the imperative language Java for the thin-client interface. the robust system architecture, and the extensibility and adaptability of the framework to any business model, are the main novelties of this work in the field of risk management information systems. this paper provides a semi-formal and non-technical explanation about the system internals.

关键词： Risk management Automatic logic units Video recording Petroleum Systems engineering and theory Scalability Availability Costs Insurance

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Behavioral synthesis of data-dominated circuits for minimal energy implementation

Behavioral synthesis of data-dominated circuits for minimal ...

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international conference on VLSI Design

作者： Xiaoyong Tang Tianyi Jiang A. Jones P. Banerjee Department of ECE Northwestern University Evanston IL USA Department of ECE University of Pittsburgh Pittsburgh PA USA

ISBN: (纸本)0769522645

this paper presents a power estimation and optimization approach in the early stage of behavioral synthesis for unscheduled data-dominated circuits. A methodology for estimating the power consumption of every module in the system is developed using an automatic construction of a novel switching table and the power table. An integer linear programming model is presented to reduce the energy consumption of the circuit through concurrent module selection, binding, and scheduling for a non-scheduled data path. Experimental results of six data-dominated benchmarks show that our technique achieves an average of 29.8% energy savings compared to a traditional area optimal synthesis algorithm where energy is not considered. Additionally, this approach consumes on the average 24.0% and 20.3% less energy compared to two other power-oriented optimization strategies respectively.

关键词： Circuit synthesis Energy consumption Hardware Flow graphs Integer linear programming Power system modeling Signal synthesis Modular construction Design optimization High level languages

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A framework for distributed and hierarchical design-for-test

A framework for distributed and hierarchical design-for-test

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international conference on VLSI Design

作者： C.P. Ravikumar R. Dandamudi V.R. Devanathan N. Haldar K. Kiran V. Kumar Bagmane Tech Park Texas Instruments (India) Private Limited Bangalore India

As we move into the system-on-chip era, test cost is becoming a significant portion of the total cost. Similarly, test synthesis, test pattern generation, pattern compression and pattern validation are consuming significant portion of the design cycle time. the volume of test generation and validation is high due to the size of the designs as well as the types of tests that are required to be run - scan test patterns for stuck-at and delay tests, logic and memory BIST patterns, IDDQ tests, burn-in tests, and several miscellaneous tests. Designs cannot be taped out without validated test patterns. At the same time, since design timing closure takes up a significant portion of the project time and the timing information is not available until late in the schedule, there is immense pressure on the DFT team to generate and validate patterns in a small time frame. this paper describes a framework for design-for-test which exploits both hierarchy and the inherent parallelism in the DFT jobs to run the jobs in a distributed computing environment so as to minimize the runtime impact.

关键词： Design for testability logic testing Costs Test pattern generators Timing System-on-a-chip System testing Delay logic design Built-in self-test

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A fuzzy logic approach for aircraft evacuation modelling

A fuzzy logic approach for aircraft evacuation modelling

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IEEE international conference on Systems Engineering

作者： M. Poudel F.M. Camino M. de Coligny J.A. thiongly LARA ENAC Toulouse France Université Toulouse II Toulouse France MIRA Université Toulouse II Toulouse France

Aircraft evacuation effectiveness is a critical issue for passenger's safety with large aircraft. New aircraft must comply with maximum exit time limits. To validate the aircraft evacuation system design and procedures, demonstration according to many different scenarios have been performed in the past. But more recently, numerical simulation tools have been developed to avoid the limitations inherent to real demonstrations. One of the main difficulties encountered by numerical simulation of evacuation operation is related with the modelling of passenger's behaviour, which is influenced by a complex mixture of socio-psychological and physical factors. this is the main point discussed in this paper.

关键词： Fuzzy logic Accidents Aircraft manufacture Air safety Numerical simulation Manufacturing industries Computer crashes Certification Aircraft propulsion Air traffic control

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Estimation of switching activity in sequential circuits using dynamic Bayesian networks

Estimation of switching activity in sequential circuits usin...

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international conference on VLSI Design

作者： S. Bhanja K. Lingasubramanian N. Ranganathan Department of Electrical Engineering University of South Florida Tampa FL USA Department of Computer Science and Engineering University of South Florida Tampa FL USA

We propose a novel, non-simulative, probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher order temporal correlations due to feedback. this model, which we refer to as the temporal dependency model (TDM), can be constructed from the logic structure and is shown to be a dynamic Bayesian network. Dynamic Bayesian networks are extremely powerful in modeling high order temporal as well as spatial correlations; it is an exact model for the underlying conditional independencies. the attractive feature of this graphical representation of the joint probability function is that not only does it make the dependency relationships amongst the nodes explicit but it also serves as a computational mechanism for probabilistic inference. We report average errors in switching probability of 0.006, with errors tightly distributed around the mean error values, on IS-CAS'89 benchmark circuits involving up to 10000 signals.

关键词： Switching circuits Sequential circuits Bayesian methods Very large scale integration State feedback Feedback circuits Predictive models Time division multiplexing logic Combinational circuits

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