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检索条件"任意字段=18th International Conference on Logic Programming"

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Formal methods for analyzing the completeness of an assertion suite against a high-level fault model

Formal methods for analyzing the completeness of an assertio...

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international conference on VLSI Design

作者： Sayanlan Das Ansuman Banerjee Prasenjit Basu Pallab Dasgupta P.P. Chakrabarti Chunduri Rama Mohan L. Fix Department of Computer Science & Engineering Indian Institute of Technology Kharagpur India DA Strategic Planning Client Platform Division Intel Corporation Folsom USA Logic and Validation Technology Intel Corporation Haifa Israel

ISBN: (纸本)0769522645

One of the emerging challenges in formal property verification (FPV) technology is the problem of deciding whether sufficient properties have been written to cover the design intent. Existing literature on FPV coverage does not solve this problem adequately, since they primarily analyze the coverage of a specification against a given implementation. On the other hand, we consider the task of determining the coverage of a formal specification against a high-level fault model that is independent of any specific implementation. We show that such a coverage analysis discovers behavioral gaps in the specification and prompts the design architect to add more properties to close the behavioral gaps. Our results establish that the coverage analysis task at this level is computationally complex, but it is possible to obtain a conservative estimate of the coverage at low cost.

关键词： Protocols Formal specifications Computer science Strategic planning logic design Costs Computational modeling Testing Writing Standards development

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Uncertain variables in decision problems for hybrid uncertain systems

Uncertain variables in decision problems for hybrid uncertai...

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IEEE international conference on Systems Engineering

作者： Z. Bubnicki Institute of Information Science and Engineering Wroclaw University of Technology Wroclaw Poland

the paper is concerned with the application of uncertain variables to complex uncertain systems containing elements with random parameters described by probability distributions and uncertain parameters described by certainty distributions given by an expert. the first part of the paper presents a general approach to decision making in the complex system under consideration. the second part is devoted to a special case: the hybrid system with a cascade structure containing random and uncertain parts. A simple example illustrates the presented approach.

关键词： Uncertain systems Decision making Information science Probability distribution Mathematical model Knowledge representation Uncertainty logic Systems engineering and theory

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Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Level-shifter free design of low power dual supply voltage C...

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international conference on VLSI Design

作者： A.U. Diril Y.S. Dhillon Abhijit Chatterjee A.D. Singh Georgia Institute of Technology Atlanta GA USA Aubum University Auburn AL USA

Usage of dual supply voltages in a digital circuit is an effective way of reducing power consumption due to the quadratic relation of supply voltage to power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. the overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of applying dual supply voltages at gate level granularity without using level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits.

关键词： threshold voltage Power supplies Low voltage Delay Energy consumption Digital circuits MOSFETs CMOS logic circuits Circuit synthesis Inverters

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Dynamic clustering using support vector learning with particle swarm optimization

Dynamic clustering using support vector learning with partic...

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IEEE international conference on Systems Engineering

作者： Jiann-Horng Lin Ting-Yu Cheng Department of Information Management I-Shou University Taiwan

this paper presents a new approach to the support vector learning for dynamic clustering based on particle swarm optimization. Support vector clustering requires solving a constrained quadratic optimization problem. this problem often involves a matrix with an extremely large number of entries, which make off-the-shelf optimization packages unsuitable. Several methods have been used to decompose the problem, of which many require numeric packages for solving the smaller subproblems. this paper gives an overview of the support vector clustering algorithm. Particle swarm optimization is discussed as an alternative method for solving a support vector clustering's quadratic programming problem. Experimental results illustrate the convergence properties of the algorithms.

关键词： Particle swarm optimization Constraint optimization Clustering algorithms Quadratic programming Matrix decomposition Packaging machines Convergence Systems engineering and theory Societies Modeling

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Efficient space/time compression to reduce test data volume and testing time for IP cores

Efficient space/time compression to reduce test data volume ...

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international conference on VLSI Design

作者： Lei Li K. Chakrabarty S. Kajihara S. Swaminathan Department Electrical & Computer Engineering Duke University Durham NC USA Department Computer Sciences & Electronics Kyushu Institute of Information Sciences Japan IBM Microelectronics Division NC USA

ISBN: (纸本)0769522645

We present 2D (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) cores. We start with a set of test cubes and use the well-known concept of scan chain compatibility to determine a small number c of tester channels that are needed to drive m scan chains (c /spl Lt/ m). Next, we exploit logic dependencies between the test data for the scan chains to design a single-level decompression circuit based on two-input gates. We refer to these procedures collectively as width (space) compression. We then determine a small set of test patterns that can provide complete fault coverage when they are applied to the circuit under test using the c tester channels; this procedure is referred to as height (time) compression. In this way, structural information about the IP cores is not necessary for fault simulation, dynamic compaction, or test generation. the hardware overhead of the proposed approach is limited to the fan-out structure and a very small number of gates between the tester-driven external scan pins and the internal scan chains. Results are presented for the ISCAS-89 benchmarks and for four industrial circuits.

关键词： Circuit testing logic testing Circuit faults Intellectual property logic design logic circuits Circuit simulation Compaction Hardware Pins

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On finding consecutive test vectors in a random sequence for energy-aware BIST design

On finding consecutive test vectors in a random sequence for...

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international conference on VLSI Design

作者： S. Zhane S.C. Seth B.B. Bhattacharya Dept. of Comput. Sci. & Eng. Nebraska-Lincoln Univ. Lincoln NE USA Department of Computer Sci. and Eng University of Nebraska-Lincoln Lincoln NE USA ACM Unit Indian Statistical Institute Calcutta India

During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying "useless" test vectors that do not contribute to fault dropping. For low-power testing, modification logic/ROM may be used to skip the LFSR states that generate useless test patterns. the overhead of extra logic increases rapidly with the number of such jumps. Since identification of useless patterns strongly depends on the order in which incremental fault simulation is performed, an elegant solution to this problem would be to find a minimum set of segments in the LFSR sequence, where each segment corresponds to a consecutive subsequence of useful test patterns. this is formulated as consecutive test cover (CTC) problem, where the objective is to optimize a cost function combining the number of segments and the number of useful test patterns. the proposed heuristic algorithm to solve the CTC problem includes a "gap" parameter to allow a controllable number of useless patterns. Experiments on ISCAS-89 benchmark circuits reveal considerable reduction in the number of segments without any degradation of mode led fault coverage.

关键词： Random sequences Built-in self-test Circuit faults logic testing Circuit testing Read only memory Test pattern generators Fault diagnosis Performance evaluation Cost function

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A verification system for transient response of analog circuits using model checking

A verification system for transient response of analog circu...

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international conference on VLSI Design

作者： Tathagato Rai Dastidar P.P. Chakrabarti National Semiconductor Corporation USA Department of Computer Science and Engineering Indian Institute of Technology Kharagpur India

ISBN: (纸本)0769522645

Conventional temporal logics like CTL (Clarke et al., 2000), used for specifying properties of digital systems are not well suited for property specification of analog systems. We present a new temporal logic for specifying properties of analog circuits. We call this logic Ana CTL (CTL for analog circuit verification). It is shown that Ana CTL is more suitable for specifying properties of analog systems than other temporal logics. the application of Ana CTL for verification of transient behavior of arbitrarily nonlinear analog circuits has been presented. the transient response of a circuit under all possible input waveforms is represented as a finite state machine (FSM), by bounding and discretizing the continuous state space of an analog circuit this FSM is created by means of repeated SPICE simulations. Algorithms have been developed to run Ana CTL queries on this discretized model. the structure of this FSM is well suited to represent the characteristics of analog circuits, and enables us to run complex queries including real-time constraints in polynomial time. the application of these methods on several real life analog circuits has been presented and we show that this system is a useful aid for detecting and debugging design errors.

关键词： Transient response Analog circuits logic circuits Digital systems Automata State-space methods SPICE Circuit simulation Polynomials Time factors

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Fuzzy logic supervision and control of distributed generators

Fuzzy logic supervision and control of distributed generator...

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CIRED 2005 - 18th international conference and Exhibition on Electricity Distribution

作者： Guillaume Rami Tuan. Tran-Uoc Nouredine Hadjsaid GIE-IDEA France GIE-IDEA - France

the decentralised production connected to electrical network has been a research theme quite developed during the last years. Indeed, several factors are responsible of such rise, technological progress in the dispersed generation fields, government economic incentives for renewable energies and finally, surely the most important factor, the deregulation permitting the possibility to sell energy provided by distributed generators (DG) connected to the transport or distribution existing networks [1]. the more common units are small-scale generation units connected on the low-voltage (LV) networks. But high penetration of that distributed energy resources (DER) may influence the operation of the network the current structure of the network is not adapted to a high insertion of DER, so the technical problems have to be identified and analysed, and studies have to be lead to improve the quality and the stability of the network using DER. this study deals with DG participations to the ancillary services and to the network operation. DR can participate to increase reliability and stability of the network, providing power closer to the consumption and they can participate to voltage control [2] [3J. this work proposes connexion of prime sources to the grid via a power electronic level. By using the inverter, it is possible to control voltage with the reactive power injected. To create a flexible and evolutive control of such system, fuzzy logic is well adapted. In the case of a high penetration of DER the control device has to be calculated considering the network states. Fuzzy logic supervision is able to adapt these control parameters depending on the error states and on its dynamic variations, regardless of the network states in terms of currents or power flows. this kind of control will permit a better stability in dynamic simulation. In this context a powerful control system for the system DER-inverter must be developed. this paper proposes a power and voltage control

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A methodology for fast vector based power supply and substrate noise analyses

A methodology for fast vector based power supply and substra...

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international conference on VLSI Design

作者： S.P. Debnath J. Sukumar H. Udaykumar Texas Instruments Inc. Bangalore India

Noise injection patterns very much depend on application scenarios. In this paper we propose a CAD methodology for a fast vector based power supply and substrate noise analyses. the proposed flow takes the switching events from a gate-level simulation and computes the time domain power/ground and substrate noise waveforms. the noise signatures are then combined with the respective extracted power supply and substrate network of the chip for a comprehensive analyses. Novel reduction techniques have been explored to achieve faster run times while maintaining good accuracy. Results of the flow can also be used for several other analyses like clock tree jitter, critical paths etc. In the end we present a case study where this method has been applied.

关键词： Power supplies Noise level Circuit noise Information analysis Noise generators logic gates Clocks Very large scale integration Libraries Analytical models

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Agent based assistance- and support in process control systems

Agent based assistance- and support in process control syste...

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IEEE international conference on Systems Engineering

作者： K. Meissner H. Hensel Department of Automation and Computer Sciences University of Applied Studies and Research Wernigerode Germany

By means of software agents, user relevant information in process control systems should be searched for and presented in a user-friendly manner. In this paper the first steps of the design of the individual agents along with the suitable framework and the basic structure for the agent communication, are presented. the emphasis of the work lies, on one hand, on the special requirements of the agent oriented software design in the process control, and on the other hand, on designing an open architecture for communication and integration of the agent in the existing structure of the system process control.

关键词： Process control Unified modeling language Software design Intelligent agent Object oriented modeling Automation Software agents Multiagent systems Software engineering programming

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