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检索条件"任意字段=18th International Conference on Logic Programming"

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Effects of technology and dimensional scaling on input loss prediction of RF MOSFETs

Effects of technology and dimensional scaling on input loss ...

引用

international conference on VLSI Design

作者： T. Das C. Washburn P.R. Mukund S. Howard K. Paradis Jung-Geau Jang J. Kolnik J. Burleson Department of Electrical Engineering Rochester Institute of Technology Rochester USA LSI Logic Corporation Fort Collins CO USA National Semiconductor Corporation Santa Clara CA USA

In this paper, we present the impact of both process and dimensional scaling on input loss (S/sub 11/) prediction of MOSFET's at GHz frequencies. We study the distributed gate effect, the non-quasi static effect, and report a drop in the resistive component of S/sub 11/ for larger fingered devices at high frequencies (> 5 GHz). We identify the boundary at which such effects start dominating. A modification to the existing lumped model is presented that tracks this effect with high accuracy. the impact of oxide thickness on S/sub 11/ in the same process and across two different processes is also presented. the study was validated with the fabrication of an extensive set of RF dimensioned transistors in LSI logic's 0.18 /spl mu/m and 0.11 /spl mu/m processes, across five different wafers.

关键词： Radio frequency MOSFETs Large scale integration MOS devices Electrical resistance measurement CMOS process CMOS technology Circuit noise Semiconductor device noise Frequency estimation

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SoC design methodology: a practical approach

SoC design methodology: a practical approach

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international conference on VLSI Design

作者： A. Jain A. Saha J. Rao Texas Instruments Inc. Dallas USA Texas Instruments Inc. Bangalore India

Today's deep sub-micron semiconductor technology has enabled large-scale integration of multi-million gates consisting of reusable intellectual property (IP), on-chip memory and user-defined logic on a single chip. the design of such SoC has introduced several challenges in terms of increased design complexity in the areas of functional verification, timing closure, physical design, signal integrity, reliability, manufacturing test and package design. this tutorial discusses a methodology that is based on the successful design of several digital dominated SoCs such as high-speed low-cost communications processors, VOP and DSL devices, high performance audio and video processors at Texas Instruments. It provides a complete breadth of digital chip design techniques. In addition, it covers some issues related to mixed-signal SoC and hierarchical design. Design tradeoffs are discussed to handle the SoC complexity, and yet meet the time-to-market demands. We review different methodologies that are followed in the industry to design these chips. Following topics are covered with examples to explain design challenges and the approaches used to address them: design planning; functional verification; design for test (DFT); synthesis, floor-planning and STA; design closure; manufacturing tests and future challenges.

关键词： Design methodology Signal design Testing Manufacturing Large scale integration Intellectual property logic Timing Packaging DSL

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Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arrays

Synthesis of reversible circuits for testing with universal ...

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international conference on VLSI Design

作者： A. Chakraborty IBM-Global Services India

Reversibility is of interest in the design of very low-power circuits; it is essential for quantum computation. this paper examines the testability of an important subclass of reversible logic circuits that are composed of k-wire controlled NOT (k-CNOT) gates. Most commonly used stuck-at fault model (both single stuck-at fault (i.e. SSF) and multiple stuck-at fault (i.e. MSF)) has been assumed to be type of fault for such circuits. We define a universal test set (UTS) for a family C(n) of n-input circuits with respect to fault model F as a family of test sets T/sub UTS/ such that each C(n) has a unique test set T(n) in T/sub UTS/ that detects all F-type faults in every member of C(n). We show that if k /spl ges/ 2 for all gates, then the n-wire reversible circuits have a UTS of size n with respect to MSFs. By synthesizing 0-CNOT (inverters) and 1-CNOT gates from 2-CNOT (Toffoli) gates this result can be extended to all circuits of interest. We also present a method for modifying an n-wire reversible circuit to reduce its UTS size to 3. By modeling a k-CNOT gate as a k-input AND gate and a 2-input EXOR gate we then examine testability for the SSF model. Noting their resemblance to classical (irreversible) Reed-Muller circuits, which are well known to be easily testable, we prove that the n-wire reversible circuits have a UTS of size n/sup 2/ + 2n + 2. Finally, we turn to the reversible counterparts of another easily-testable classical circuit family, iterative logic arrays (ILAs). We define d-dimensional reversible ILAs (RILAs) and prove that they require a constant number test vectors irrespective of array length under the single cell fault (i.e. SCF) model; this number is determined by the size of the RILA cell's state table.

关键词： Circuit testing logic testing logic arrays Circuit synthesis logic circuits Circuit faults Quantum computing Electrical fault detection Fault detection Inverters

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Modeling usable & reusable transactors in system Verilog

Modeling usable & reusable transactors in system Verilog

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international conference on VLSI Design

作者： J. Bergeron Modeling Usable & Reusable Transactors in SystemVerilog Synopsys Inc. USA

Summary form only given. Transactors, also known as bus-functional models, have traditionally been modeled using a procedural interface (API). Commands were provided to use every feature available in the transactor. Several commands were often necessary to configure the transactor or to execute the simplest transaction. If the transactor did not provide a feature required by a particular device under test (DUT) or testcase, it had to be modified or rewritten. By using an object-oriented approach for configuration and interfacing, transactors can easily be used out-of-the-box. A few lines are all that is necessary to create valid random stimulus to a DUT or report observed response to a scoreboard. the use of callback methods eliminates the need for a complex and ever-evolving API. Instead of creating yet-another programming language, it leverages the power of system Verilog to extend the functionality of a transactor in ways the original author may not have conceived. Without modification, a transactor can thus be used and reused effectively. Transactors can also be modeled in an extensible fashion. Extensible transactors allow users to define entirely new transactions and commands, should the ones provided by the original implementation prove insufficient. Usability and reusability of transactors does not happen by accident. With careful design and consistent use model, transactors can be written to meet the stringent demands of different testcases on different design under verification. this paper describes how to properly use the object-oriented features of system Verilog to model transactions and transactors that execute them. Designers, used to a procedural programming model, will learn how to approach a transactor modeling problem using the object-oriented approach. Software engineers, used to a traditional object-oriented programming model, will learn how to adapt their methods to the special requirements of constrained-random verification. this paper present

关键词： Hardware design languages Object oriented modeling Testing Object oriented programming Writing Industrial training Guidelines Computer languages Power system modeling Usability

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Software comprehension/maintenance: an introductory course

Software comprehension/maintenance: an introductory course

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IEEE international conference on Systems Engineering

作者： M.A. Austin M.H. Samadzadeh Techrizon USA Computer Science Department Oklahoma State University USA

Software maintenance is a costly problem for industry, typically taking up to 50-75% of the cost of software development (IS). Traditional computer science programs often do not prepare students to face this problem. Since a large part of software maintenance is software comprehension, better comprehension methods are the answer to the problem. Students often do not know how to comprehend already written code and do not know how to work in groups. this paper proposes a course that has been designed to better prepare students for work in the area of software maintenance by teaching them software comprehension methods. the course includes best practices, a large-scale project, and focuses primarily on code comprehension methods.

关键词： Software maintenance programming profession Computer science Costs Computer industry Flow graphs Area measurement Software measurement Software engineering Education

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Improved layout-driven area-constrained timing optimization by net buffering

Improved layout-driven area-constrained timing optimization ...

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international conference on VLSI Design

作者： R. Murgai Fujitsu Laboratories of America Inc. Sunnyvale CA USA

With the advent of deep sub-micron technologies, interconnect loads and delays have become significant, and layout-driven synthesis has become the need of the day. However, due to the tight layout constraints (e.g., area availability, congestion), only layout-friendly logic transforms such as net buffering and gate resizing can be used effectively. In this paper, we address the problem of minimizing the delay of a mapped, roughly-placed and globally-routed design by buffer insertion and/or deletion without violating the local area constraints imposed by the layout. To the best of our knowledge, only one earlier work has addressed this problem (Murgai, 2000). Although the algorithm presented by Murgai (2000) is optimum for a single net, it has worst-case exponential run-time and is not suitable for large nets. In this paper, we present techniques to make this algorithm practical by improving the run-time without sacrificing the quality. We present a condition called ONPRB, which, if satisfied by the net, improves the worst case runtime complexity to quadratic, without causing a loss in optimality. A study of industrial designs showed that up to 80% of the critical nets satisfied the ONPRB condition. To further reduce the run-time, we propose a technique to convert a net into one that satisfies this condition. Experiments on industrial designs show that the proposed scheme gives up to 12.5 times speed-up over (Murgai, 2000), without sacrificing the design quality (i.e., final delay and area).

关键词： Timing Delay Routing Circuits Runtime Design optimization logic design Constraint optimization Wire Laboratories

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Optimizing SoC manufacturability

Optimizing SoC manufacturability

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18th international conference on VLSI Design: Power Aware Design of VLSI Systems

作者： Zorian, Yervant Virage Logic Corp. IEEE Computer Society National Academy of Sciences of Armenia IEEE

Every new semiconductor technology node provides further miniaturization and higher performance, thus increasing the functions that electronic products could offer. Although adding such new functions do benefit the end-user, but they also necessitate finer and denser semiconductor fabrication processes, which make chips more susceptible to defects. Todayâ&euro™s nanometer technologies are reaching defect susceptibility levels that result in lowering the manufacturing yield and reliability, and hence lengthening the production ramp-up period, and therefore the time to volume (TTV). the impact on manufacturability and TTV is very critical for the semiconductor industry. It puts the conventional IC realization flow at an impasse. In fact, every single phase in the IC realization flow has an impact yield and reliability, including the design phase, prototyping, volume fabrication, test, assembly, packaging, failure analysis and even the post-production life cycle of the chip. In order to optimize yield and reach acceptable TTV levels, the semiconductor industry needs to adopt advanced manufacturability optimization solutions. these solutions need to be implemented at different phases of the chip realization flow. the conventional semiconductor manufacturing infrastructure, i.e. the external equipment and processes, alone are insufficient to handle such advanced solutions;supplemental on-chip infrastructure is needed. To optimize manufacturability, the industry has recently introduced a range of embedded intellectual-property (IP) blocks, called infrastructure IP. these are meant for inclusion into IC design and utilized during the different phases of product realization. Semiconductor IP is well known for the last decade. Most of the known IP blocks, though, are functional ones, such as embedded processor, memory, analog, or FPGA cores. Whereas, Infrastructure IP (I-IP) is not functional, i.e. does not contribute to the normal functionality of a given IC. Rather, I-IP i

关键词： Integrated circuit layout

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ESL - the next leadership opportunity for India?

ESL - the next leadership opportunity for India?

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international conference on VLSI Design

作者： A. Naumann CoWare Inc. Germany

Summary form only given. this paper lectures on the increasingly critical role played by electronic system level (ESL) design tools in the development of the complex system-on-chip (SoC) devices that are now the indispensable engines of advanced consumer and communications products. Drawing upon his experience in managing CoWare, which has world-class software development resources in India, the author argues that ESL tool development expertise can be an effective differentiator for Indian software engineering. this paper discusses the growing impact of SoC technology on the global electronics market, and the factors driving it. In particular, contrary to the conventional wisdom, the design cost per gate continues to fall - because rising mask costs are more than offset by the massive increase in the number of gates per chip. this increase in gate capacity presents SoC designers not only with a significant market opportunity, but also with a serious design challenge - how to integrate so much functionality into one chip without the multiple re-spins that destroy a product's time to market and bury its design budget. Also discussed is the ESL design methodology, and it is argued that the adoption of such a methodology is a pre-requisite for meeting this SoC design challenge. this paper argues that Indian engineers - with their proven expertise in software modelling and development - can occupy a pole position in this new industrial revolution.

关键词： Costs System-on-a-chip Engines Engineering drawings Resource management Software development management Engineering management programming Software engineering Consumer electronics

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Using contrapositive law in an implication graph

Using contrapositive law in an implication graph

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international conference on VLSI Design

作者： K.K. Dave V.D. Agrawal M.L. Bushnell ATI Research Inc. Yardley PA USA Department of ECE Aubum University Auburn AL USA Department of ECE Rutgers University Piscataway NJ USA

Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new "oring" node structure to represent partial implications in a graph. the oring node is the contrapositive of the previously used "anding" node. An n-input gate requires one oring and one anding nodes to represent all partial implications. this implication graph is shown to be more complete and more compact compared to the previously published (n+1) anding node graph. Introduction of the new oring node finds more redundancies using the transitive closure method. the second contribution of the present work is a set of new algorithms to update transitive closure for every newly added edge in the implication graph associated with anding and oring nodes. For the ISCAS'85 benchmark circuit c1908, the new graph identifies 5 out of a total of 7 redundant faults. the best known previous implication graph procedure could only identify 2 redundant faults. We analyze the unidentified redundant faults and suggest a possible improvement.

关键词： Circuit faults Redundancy Circuit testing Fault diagnosis Digital circuits logic Circuit synthesis Signal synthesis Automatic test pattern generation Circuit analysis

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On physical-aware synthesis of vertically integrated 3D systems

On physical-aware synthesis of vertically integrated 3D syst...

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international conference on VLSI Design

作者： M. Mukherjee R. Vemuri Department of ECECS University of Cincinnati Cincinnati OH Department of ECECS University of Cincinnati Cincinnati OH USA

Vertical integration of active device layers in the third dimension makes room for significant reduction in interconnect lengths leading to decrease in both delay and power consumption associated with interconnects. this characteristic can be well leveraged only by judicious layer assignment of active devices. To address layer assignment as a part of behavioral synthesis, we proposed a 0-1 linear program formulation to simultaneously schedule, bind and perform layer assignment for synthesis of vertically integrated 3D systems. In these systems, inter-stratal communication occurs through inter-layer vias that have higher resistivity and capacitance. In this paper, we propose a trade-off between reducing the total interconnect delay in critical paths while reducing the inter-stratal communication. three different objective models are proposed and their combinations examined to find the most suitable methodology to achieve these goals. A power gradient is proposed between layers to address the thermal issues associated with these systems that have been shown to be of concern. Results shows a significant reduction in total interconnect lengths compared to a traditional two-dimensional implementation. the examination of the various proposed optimization objectives indicate that a combination of communication minimization and critical path optimization leads to the best synthesis results for a range of benchmarks.

关键词： Integrated circuit interconnections Power system interconnection High level synthesis Delay Temperature Power dissipation logic thermal resistance Energy consumption Conductivity

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