this paper presents a computer-aided system for scheduling student computer consultants at remote computing sites in an academic environment. the system takes consultants' preferred availability input via on-line ...
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the KR realization (see S. Kundu and S. M. Reddy, Proc. 18th Int. Fault-Tolerant Computing Symp., 1988, pp. 220-225) was proposed withthe aim of designing testable CMOS combinational circuits using only primitive gat...
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ISBN:
(纸本)0818689625
the KR realization (see S. Kundu and S. M. Reddy, Proc. 18th Int. Fault-Tolerant Computing Symp., 1988, pp. 220-225) was proposed withthe aim of designing testable CMOS combinational circuits using only primitive gates and no extraneous hardware. It is shown that for some useful Boolean functions the size of the KR realization is exponential in the number of input variables. the author presents a testable realization of a CMOS combinational circuit, with respect to FET (field-effect-transistor) stuck-open faults, named FM-CMOS. It uses only two-input multiplexers and, to an extent, addresses the size-problem of the KR realization. More specifically, it is shown that for some useful Boolean functions for which the size of the KR realization is exponential in the number of input variables the size of the FM-CMOS realization is polynomial in the number of input variables. For this reason, it is proposed that the FM-CMOS realization be used in conjunction withthe KR realization. the results are applied to design a testable n-b CMOS adder that uses only O(n) FETs.
the game of Sprouts has intrigued mathematicians for nearly twenty years. this paper describes a representation scheme which simplifies much of the geometry of the game. Using this representation, we develop a Prolog ...
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the objective of the research reported in this paper was to greatly simplify the programming task while maintaining all of the constraints normally imposed. this was accomplished by developing a transformation algorit...
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ISBN:
(纸本)0871712776
the objective of the research reported in this paper was to greatly simplify the programming task while maintaining all of the constraints normally imposed. this was accomplished by developing a transformation algorithm for computer solution. A large part of the programming work load is then shifted from the system programmer to the computer. Withthis system it is only necessary to position the torch at each programmed position such that it is at the desired orientation relative to the weld joint. the positioner may be in any convenient position, and the wire guide for externally fed filler metal may be arbitrarily positioned as well. the methodology described has led to several results and conclusions which are listed.
We present a Josephson 2-bit arithmetic logic unit(ALU) which consists of a 4JL-gate family. the circuit was fabricated using a Nb/Al-oxide/Nb junction process.
ISBN:
(纸本)493081314X
We present a Josephson 2-bit arithmetic logic unit(ALU) which consists of a 4JL-gate family. the circuit was fabricated using a Nb/Al-oxide/Nb junction process.
Suitable configurations of Josephson logic LSIs for computer applications are discussed. It is indicated that gate arrays are particularly suitable for realizing custom logic functions because of their simplified desi...
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ISBN:
(纸本)493081314X
Suitable configurations of Josephson logic LSIs for computer applications are discussed. It is indicated that gate arrays are particularly suitable for realizing custom logic functions because of their simplified design capability. A Josephson-threshold-logic circuit is proposed to form standard logic functions in the optimal structure. Two Josephson logic LSIs are developed: a 3K gate array and a 4 multiplied by 4 bit multiplier. the switching times of the OR and AND gate on the gate array were 15ps and 30ps, respectively. A critical-path delay of 210ps was attained on the multiplier.
A new GaAs logic circuitry, named 'Schottky diode Level shifter Capacitor coupled FET logic (SLCF)', has been developed. It has driver DFETs and a load DFET in the logic stage, in front of which a level shifti...
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ISBN:
(纸本)493081314X
A new GaAs logic circuitry, named 'Schottky diode Level shifter Capacitor coupled FET logic (SLCF)', has been developed. It has driver DFETs and a load DFET in the logic stage, in front of which a level shifting stage including a Schottky diode is connected. the main feature of the circuit is that the Schottky diode performs level shifting as well as feedforward capacitor coupling of the input signal. It offers high-speed, 40 ps/gate, and a larger noise margin than DCFL, with around 1 mw/gate power consumption, which ensures reliable and stable GaAs LSI operation with 4K-8K gate complexity.
Authors present a method for efficient mechanical reasoning about finite state concurrent systems under a broad class of generalized fairness assumptions. the global state graph of such a system can be viewed as a fin...
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Authors present a method for efficient mechanical reasoning about finite state concurrent systems under a broad class of generalized fairness assumptions. the global state graph of such a system can be viewed as a finite (Kripke) structure, and an efficient (in fact, linear time) model checking algorithm is described for determining if a given structure is a model of a specification expressed in a propositional branching time temporal logic. the logic is called Fair Computation Tree logic (FCTL).
this paper illustrates the application of a recent technology - syntax-directed editors and interactive integrated programming environments - to robot programming. In particular, a syntax-directed editor generator is ...
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this paper illustrates the application of a recent technology - syntax-directed editors and interactive integrated programming environments - to robot programming. In particular, a syntax-directed editor generator is presented referring to an experimental robot language for assembly tasks. 21 refs.
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