A general simulation program for LSI devices is described. the program provides functional simulation capability as well as the ability to simulate chip interface timing. Chip modeling utilizes chip input/output speci...
详细信息
ABLE, an array-based linguistic editor, is a layout modeling language for storage/logic arrays (SLA's) that is based on the LISP programming language. this paper describes ABLE's design, presents an ABLE layou...
详细信息
ABLE, an array-based linguistic editor, is a layout modeling language for storage/logic arrays (SLA's) that is based on the LISP programming language. this paper describes ABLE's design, presents an ABLE layout program, and evaluates ABLE's usefulness in SLA-based circuit design. ABLE embodies a linguistic approach to computer-aided design (CAD) for very large scale integrated (VLSI) circuits; digital system designers can represent SLA-based integrated circuits as relatively abstract and highly flexible ABLE layout programs. the informational complexity of VLSI design can be reduced both by using straightforward CAD algorithms based on the SLA structured logic layout technique, and by using user-definable procedural models within LISP-based layout modeling languages.
A general simulation program for LSI devices is described. the program provides functional simulation capability as well as the ability to simulate chip interface timing. Chip modeling utilizes chip input/output speci...
A general simulation program for LSI devices is described. the program provides functional simulation capability as well as the ability to simulate chip interface timing. Chip modeling utilizes chip input/output specifications and timing diagrams. Construction and coding of the model is a process very much akin to assembly language programming. GSP is a program suitable for the simulation of LSI devices as it allows for a manageable amount of detail in model descriptions and can simulate with an efficiency that is adequate for system validation activities.
Multiple test generation algorithms and techniques described in this paper have been integrated into a unified system which has successfully produced tests for unpartitioned LSSD logic structures of up to 50,000 logic...
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Multiple test generation algorithms and techniques described in this paper have been integrated into a unified system which has successfully produced tests for unpartitioned LSSD logic structures of up to 50,000 logic gates. the design concepts behind the creation of a unified system are presented, as are actual results obtained on large logic structures. System usability was significantly enhanced by the same concepts that facilitated the integration of multiple algorithms and techniques.
In the last five years, there has been rapid growth in logic and memory chip circuit density. the number of different digital processors and the typical size of such processors has also grown. With all this growth, al...
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In the last five years, there has been rapid growth in logic and memory chip circuit density. the number of different digital processors and the typical size of such processors has also grown. With all this growth, alternatives in VLSI design style as well as packaging have to be considered. these consist, on the one hand, of powerful automated placement and wiring routines, indispensable on large regular package images, and, on the other, of techniques facilitating rapid, interactive adaptation of functional logic design to the layout and interconnection of "macros" on large chips. Some results from study of each method are presented.
Withthe advent of large scale integration (LSI and VLSI), logic circuit densities per chip have grown to hundreds and thousands. the arrangement of interconnected logic circuits of different sizes and shapes poses a ...
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As digital integrated circuits become more complex, Computer Aided Design (CAD) must support more hierarchical design methods. Top-down design is supported in logic simulators by the inclusion of functional models. th...
As digital integrated circuits become more complex, Computer Aided Design (CAD) must support more hierarchical design methods. Top-down design is supported in logic simulators by the inclusion of functional models. the SAndia logic Simulator (SALOGS) has functional modelling capability but until now only as FORTRAN subroutines. the new Structural Interface to the SALOGS Language (SISL) allows the design engineer access to the functional modelling capabilities without requiring the associated programming skills. the SISL syntax is described and a sample functional model library is presented.
As digital integrated circuits become more complex, Computer Aided Design (CAD) must support more hierarchical design methods. Top-down design is supported in logic simulators by the inclusion of functional models. th...
详细信息
As digital integrated circuits become more complex, Computer Aided Design (CAD) must support more hierarchical design methods. Top-down design is supported in logic simulators by the inclusion of functional models. the SAndia logic Simulator (SALOGS) has functional modeling capability but until now only as FORTRAN subroutines. the new Structural Interface to the SALOGS Language (SISL) allows the design engineer access to the functional modelling capabilities without requiring the associated programming skills. the SISL syntax is described and a sample functional model library is presented.
ABLE, an array-based linguistic editor, is a layout modeling language for storage/logic arrays (SLA's) that is based on the LISP programming language. this study describes ABLE's design, presents an ABLE layou...
详细信息
ABLE, an array-based linguistic editor, is a layout modeling language for storage/logic arrays (SLA's) that is based on the LISP programming language. this study describes ABLE's design, presents an ABLE layout program, and evlauates ABLE's usefulness in SLA-based circuit design. ABLE embodies a linguistic aproach to computer-aided design (CAD) for very large scale integrated (VLSI) circuits;digital system designers can represent SLA-based integrated circuits as relatively abstract and highly flexible ABLE layout programs.
A general simulation program for LSI devices is described. the program provides functional simulation capability as well as the ability to simulate chip interface timing. Chip modeling utilizes chip input/output speci...
详细信息
A general simulation program for LSI devices is described. the program provides functional simulation capability as well as the ability to simulate chip interface timing. Chip modeling utilizes chip input/output specifications and timing diagrams. Construction and coding of the model is a process very much akin to assembly language programming. GSP is a program suitable for the simulation of LSI devices as it allows for a manageable amount of detail in model descriptions and can simulate with an efficiency that is adequate for system validation activities.
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