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Design of Approximate DNN Accelerators through Framework-Based and Circuit-Level Techniques 18

Design of Approximate DNN Accelerators through Framework-Bas...

引用

18th international Workshop on Cellular Nanoscale Networks and their Applications (CNNA)

作者： Leon, Vasileios Xydis, Sotirios Lentaris, George Soudris, Dimitrios Natl Tech Univ Athens Sch Elect & Comp Engn Athens Greece

ISBN: (纸本)9798350308938;9798350308921

Deep Neural Networks (DNNs) are considered as one of the state-of-the-art approaches for providing excellent accuracy in Artificial Intelligence tasks. However, their increased computing & memory intensity challenges their efficient implementation. Among the examined solutions for improved efficiency, Approximate computing exploits their error resilience to address the high energy demands and/or performance bottlenecks of DNN accelerators. In this context, we demonstrate two design approaches for generating approximate DNN hardware accelerators. Our framework-based method applies coarse- and fine-grained approximation at different levels of the DNN architecture, while our circuit-level method integrates various approximations in the HDL development of parallel DNN architectures.

关键词： Approximate computing computer Arithmetic Approximate Multipliers Deep Neural Networks Hardware Design Hardware Accelerators ASICs FPGAs TensorFlow.

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Using Logging-on-Write to Improve Non-Volatile Memory Checkpoints via Processing-in-Memory 35

Using Logging-on-Write to Improve Non-Volatile Memory Checkp...

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35th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Kruger, Kleber Pannain, Ricardo Azevedo, Rodolfo Univ Estadual Campinas Inst Comp Campinas Brazil

ISBN: (纸本)9798350305487

NVM architectures must keep consistent data in case of failures, a property called crash consistency. A common way to do so is by checkpoint mechanisms. However, most of the strategies developed have performance and usability problems. Among main limitations are non-software-transparent strategies, the addition of logging operations in the critical execution path, and increased writes to NVM, resulting in significant bandwidth usage between processor and memory. DONUTS solves these problems by a hardware mechanism that provides crash consistency via checkpoints integrated into cache replacement policy using Processing-in-Memory to perform logging operations. Its approach reduces writes from the processor's memory controller and the NVM external bandwidth usage but generates unnecessary log entries. this paper expands DONUTS to a multi-core scenario evaluating two processing-in-memory strategies. the first logs during read operations, and the second uses a new lazy strategy to log data exclusively on write operations when these operations are effectively needed. Finally, we compare runtime performance, log rate, energy consumption, and memory space. Results show that our new logging-on-write strategy maintained the DONUTS runtime performance but reduced energy consumption in multi-core applications by around 33% due to an average reduction of 42% in log operations. Also, the new strategy generates a checkpoint size 5x smaller than the previous system, maximizing the use of NVM. Compared to other systems, DONUTS presented an average overhead of 1% to 3% against up to 7% of previous software-transparent better-performing projects.

关键词： processing-in-memory in-memory computing non-volatile memory checkpointing crash consistency

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Assessing the performance of an architecture-aware optimization tool for neural networks 35

Assessing the performance of an architecture-aware optimizat...

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35th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Marichal, Raul Dufrechou, Ernesto Ezzatti, Pablo Fac Ingn Inst Comp Montevideo Uruguay

ISBN: (纸本)9798350381603

the important growth in the demand for Neural Network solutions has created an urgent need for efficient implementations across a wide array of environments and platforms. As industries increasingly rely on AI-driven technologies, optimizing the performance and effectiveness of these networks has become crucial. While numerous studies have achieved promising results in this field, the process of fine-tuning and identifying optimal architectures for specific problem domains remains a complex and resource-intensive task. As such, there is a pressing need to explore and evaluate techniques that can improve this optimization process, reducing costs and time-to-deployment while maximizing the overall performance of Neural Networks. this work focuses on evaluating the optimization process of NetAdpat for two neural networks on an Nvidia Jetson device. We observe a performance decay for the larger network when the algorithm tries to meet the latency constraint. Furthermore, we propose potential alternatives to optimize this tool. Particularly, we propose an alternative configuration search procedure that allows us to enhance the optimization process, achieving speedups of up to similar to 7x.

关键词： efficient computing neural network optimizations edge devices heterogeneous computing NetAdapt

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Proceedings - 2024 IEEE international symposium on high-performance computer architecture, HPCA 2024

Proceedings - 2024 IEEE International Symposium on High-Perf...

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30th IEEE international symposium on high-performance computer architecture, HPCA 2024

ISBN: (纸本)9798350393132

the proceedings contain 78 papers. the topics discussed include: exploitation of security vulnerability on retirement;GadgetSpinner: a new transient execution primitive using the loop stream detector;uncovering and exploiting AMD speculative memory access predictors for fun and profit;Revet: a language and compiler for dataflow threads;an optimizing framework on MLIR for efficient FPGA-based accelerator generation;Celeritas: out-of-core based unsupervised graph neural network via cross-layer computing 2024;MEGA: a memory-efficient GNN accelerator exploiting degree-aware mixed-precision quantization;Gemini: mapping and architecture co-exploration for large-scale DNN Chiplet accelerators;STELLAR: energy-efficient and low-latency SNN algorithm and hardware co-design with spatiotemporal computation;and MIMDRAM: an end-to-end processing-using-DRAM system for high-throughput, energy-efficient and programmer-transparent multiple-instruction multiple-data computing.

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ECSSD: Hardware/Data Layout Co-Designed In-Storage-computing architecture for Extreme Classification 23

ECSSD: Hardware/Data Layout Co-Designed In-Storage-Computing...

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50th Annual international symposium on computer architecture (ISCA)

作者： Li, Siqi Tu, Fengbin Liu, Liu Lin, Jilan Wang, Zheng Kang, Yangwook Ding, Yufei Xie, Yuan Univ Calif Santa Barbara Santa Barbara CA 93106 USA Hong Kong Univ Sci & Technol Hong Kong Peoples R China Rensselaer Polytech Inst Troy NY USA Samsung Semicond Inc San Jose CA USA Alibaba Grp DAMO Acad Sunnyvale CA USA

ISBN: (纸本)9798400700958

With the rapid growth of classification scale in deep learning systems, the final classification layer becomes extreme classification with a memory footprint exceeding the main memory capacity of the CPU or GPU. the emerging in-storage-computing technique offers an opportunity on account of the fact that SSD has enough storage capacity for the parameters of extreme classification. However, the limited performance of naive in-storage-computing schemes is insufficient to support the heavy workload of extreme classification. To this end, we propose ECSSD, the first hardware/data layout co-designed in-storage-computing architecture for extreme classification, based on the approximate screening algorithm. We propose an alignment-free floating-point MAC circuit technique to improve the computational ability under the limited area budget of in-storage-computing schemes so that the computational ability can match SSD's high internal bandwidth. We present a heterogeneous data layout design for the 4/32-bit weight data in the approximate screening algorithm to avoid data transfer interference and further utilize the internal DRAM bandwidth of SSD. Moreover, we propose a learning-based adaptive interleaving framework to balance the access workload in each flash channel and improve channel-level bandwidth utilization. Putting them together, our ECSSD achieves 3.24-49.87x performance improvements compared with state-of-the-art baselines.

关键词： In-storage-computing architecture Extreme classification

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Exploring the Serverless First Strategy in Cloud Application Development 35

Exploring the Serverless First Strategy in Cloud Application...

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35th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Cavalheiro, Adriano Prado Schepke, Claudio Fed Univ Pampa Alegrete PPGES Grad Program Software Engn Alegrete Brazil

ISBN: (纸本)9798350381603

this paper explores the Serverless First strategy in cloud application development. Serverless computing has gained popularity due to its flexibility and scalability. In our work, we provide a systematic review of the literature about the Serverless paradigm in cloud computing and an evaluation of the advantages of this approach by performing a comparative analysis among three ways for the implementation of an application: AWS Lambda, AWS Lambda with Chalice framework, and the traditional form using the Flask framework. the literature review results show the gains in scaling, cost reduction, and ease of maintenance achieved with the Serverless First strategy. However, some limitations and challenges were also highlighted, such as the greater complexity of the environment, less control over resources, resource limitations imposed by the cloud provider, and difficulties in debugging and managing the infrastructure. the case study demonstrates in practice that the Chalice framework provided the most straightforward and rapid implementation, the AWS Lambda without Chalice offered greater flexibility and control, and the Flask version allowed local testing and total control but required more manual setup and lacked automatic scalability.

关键词： Serverless First Function as a Service Serverless computing Serverless architecture Serverless Applications Software Development Cloud computing Cloud Services

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MIRAGE: Quantum Circuit Decomposition and Routing Collaborative Design using Mirror Gates 30

MIRAGE: Quantum Circuit Decomposition and Routing Collaborat...

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30th IEEE international symposium on high-performance computer architecture (HPCA)

作者： McKinney, Evan Hatridge, Michael Jones, Alex K. Univ Pittsburgh Dept Elect & Comp Engn Pittsburgh PA 15260 USA Univ Pittsburgh Dept Phys & Astron Pittsburgh PA 15260 USA

ISBN: (纸本)9798350393132;9798350393149

Building efficient large-scale quantum computers is a significant challenge due to limited qubit connectivities and noisy hardware operations. Transpilation is critical to ensure that quantum gates are on physically linked qubits, while minimizing SWAP gates and simultaneously finding efficient decomposition into native basis gates. the goal of this multifaceted optimization step is typically to minimize circuit depth and to achieve the best possible execution fidelity. In this work, we propose MIRAGE, a collaborative design and transpilation approach to minimize SWAP gates while improving decomposition using mirror gates. Mirror gates utilize the same underlying physical interactions, but when their outputs are reversed, they realize a different or mirrored quantum operation. Given the recent attention to root iSWAP as a powerful basis gate with decomposition advantages over CNOT, we show how systems that implement the iSWAP family of gates can particularly benefit from mirror gates. Further, MIRAGE uses mirror gates to reduce routing pressure and reduce true circuit depth instead of just minimizing SWAPs. We explore the benefits of decomposition for root iSWAP and (4)root iSWAP using mirror gates, including both expanding Haar coverage and conducting a detailed fault rate analysis trading off circuit depth against approximate gate decomposition. We also describe a novel greedy approach accepting mirror substitution at different aggression levels within MIRAGE. For iSWAP systems that use square-lattice topologies, MIRAGE provides an average of 29.6% reduction in circuit depth by eliminating an average of 59.9% SWAP gates, with a relative decrease in infidelity of 28%. MIRAGE also improves circuit depth and decreases relative infidelity by 25% and 21% for CNOT-based and 23% and 19% SYC-based machines, respectively.

关键词： quantum circuit optimization quantum circuit routing quantum computing

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high performance computing Infrastructure in Technical University Research 18

High Performance Computing Infrastructure in Technical Unive...

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IEEE 18th international Conference on Intelligent computer Communication and Processing (ICCP)

作者： Gorgan, Dorian Tech Univ Cluj Napoca Dept Comp Sci Cluj Napoca Romania

ISBN: (纸本)9781665464376

A technical university needs high performance computing resources to support the research activity carried out by interdisciplinary teams, through heterogeneous, various and flexible configurations. the CloudUT infrastructure has been designed and developed to meet the requirements and performances necessary for research projects in the scientific and engineering fields specific to the Technical University of Cluj-Napoca such as big data, artificial intelligence, spatial data, satellite data, internet of things, complex simulation, and computer assisted design. this paper analysis and highlight the challenges and issues on finding efficient solutions for the distributed architecture, parallel computing, massive data, flexible architectures, virtualization, cloud applications and services for covering a large range of technical domains of engineering such as mechanics, automation and computers, civil and building services, electric, architecture and urban planning, electronics, robotics, and mechatronics.

关键词： high performance computation cloud infrastructure technical university research activity interdisciplinary research

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Spiro: Order-Preserving Visualization in high performance computing Monitoring 18th

Spiro: Order-Preserving Visualization in High Performance Co...

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18th international symposium on Visual computing (ISVC)

作者： Dang, Tommy Nguyen, Ngan V. T. Li, Jie Sill, Alan Chen, Yong Texas Tech Univ Lubbock TX 79409 USA

ISBN: (纸本)9783031479687;9783031479694

As high-performance computing (HPC) is moving closer to entering the exascale era, monitoring HPC systems is becoming increasingly important and continuously more complex. the innovations in interactive visualization provide tremendous assistance in presenting complex HPC data to be more comprehensible and promote the roles of humans in the analysis process. With the larger number of system components in the monitoring tasks, representing them in order requires a scalable mechanism for handling multiple visual elements and simultaneously preserving the context of ordering. In this paper, we propose a novel method for utilizing the spiral layout for order-preserving visualization in HPC monitoring, called Spiro. To demonstrate the effectiveness and usefulness of Spiro, we present the case studies of the application to a real-world temporal, multivariate HPC dataset.

关键词： high-performance computing Center RESTful API Time-Series Data Analysis Spiral Layout Multivariate Clustering Multidimensional Data Visualization

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Probabilistic Local Equivalence Certification for Robustness Evaluation 18th

Probabilistic Local Equivalence Certification for Robustness...

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18th international symposium on Visual computing (ISVC)

作者： Bond, Jacob Gupta, Siddhartha Elvitigala, thanura Gen Motors Co Warren MI 48092 USA

ISBN: (纸本)9783031479687;9783031479694

To evaluate the robustness of non-classifier models, we propose probabilistic local equivalence, based on the notion of randomized smoothing, as a way to quantitatively evaluate the robustness of an arbitrary function. For a given function f, probabilistic local equivalence evaluates whether, when sampling a normally-distributed point x' in a neighborhood of a point x, there is a probability > 0.5 that f(x') is equivalent to f(x), according to a user-defined notion of equivalence. We use probabilistic local equivalence to evaluate the effect of data augmentation methods for improving robustness, including adversarial training, on a model's performance. We also use probabilistic local equivalence to evaluate the effect on robustness of model architecture, number of parameters, pre-training, quantization, and other model properties.

关键词： computer Vision Robustness Evaluation

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