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18th IEEE symposium on computer-Based Medical Systems

作者： Boccia, V Guarracino, MR D'Amore, L Laccetti, G CNR ICAR Inst High Performance Comp & Networking Naples Branch I-80125 Naples Italy

ISBN: (纸本)0769523552

A key issue in designing applications codes which are able to effectively take advantage of grid computing environments is to deal and manage all the software components complexity, this is even more true for medical imaging applications. We are concerned with development of a medical imaging PSE for advanced and grid computing environments. Specifically, MedIGrid is a distributed application for the management, processing and visualization of biomedical images that integrates a set of software and hardware components, or, more specifically, a set of grid collaborative applications useful to nuclear doctors. It results from the interaction of computing scientists devoted to the design and deployment of new tomographic reconstruction algorithms techniques, computer scientists researchers in the field of distributed and parallel architectures and physicians involved in nuclear medicine. We'll describe MedIGrid general architecture, as well as improvements and enhancements, essentially regarding the semantic power of the GUI (the Portal) (its language and its realization), and the entire phase of monitoring and migration of the parallel computational kernel for images reconstruction, mainly based on a performance contract inked taking into account historical performances and an ad hoc developed performance model.

关键词： Medical imaging

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Architectural Support for Synchronization-Free Deterministic Parallel Programming

Architectural Support for Synchronization-Free Deterministic...

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18th IEEE international symposium on high-performance computer architecture (HPCA)

作者： Segulja, Cedomir Abdelrahman, Tarek S. Univ Toronto Edward S Rogers Sr Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781467308243;9781467308267

We propose a novel synchronization mechanism called versioning. It dynamically establishes a deterministic order of memory accesses in parallel programs that have serial semantics, in a way that is transparent to the program m er. this order is created in a distributed manner and is enforced by monitoring memory accesses and stalling threads if necessary. Versioning gives rise to parallel programming models in which programmers need not explicitly synchronize threads and only need to specify shared data, which greatly simplifies parallel programming. However, versioning introduces overheads and thus demands architectural support. We describe versioning and the architectural support it needs. We also propose one parallel programming model that utilizes versioning and use it to parallelize 13 benchmark applications. We build an FPGA prototype of a multiprocessor system with versioning support and show that good parallel speedups are obtained. Our analysis shows minimal impact of versioning, both in terms of timing over-heads and in terms of additional hardware.

关键词： Parallel programming thREADS Stalling computer personnel deterministic

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Dual-thread speculation: A simple approach to uncover thread-level parallelism on a simultaneous multithreaded processor

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international JOURNAL OF PARALLEL PROGRAMMING 2008年第2期36卷 166-183页

作者： Warg, Fredrik Stenstrom, Per Nema Labs AB Chalmers Innovat S-40278 Gothenburg Sweden Chalmers Univ Technol S-41296 Gothenburg Sweden

As chip multiprocessors with simultaneous multithreaded cores are becoming commonplace, there is a need for simple approaches to exploit thread-level parallelism. In this paper, we consider thread-level speculation as a means to reap thread-level parallelism out of application binaries. We first investigate the tradeoffs between scheduling speculative threads on the same core and on different cores. While threads contend for the same resources using the former approach, the latter approach is plagued by the overhead for inter-core communication. Despite the impact of resource contention, our detailed simulations show that the first approach provides the best performance due to lower inter-thread communication cost. the key contribution of the paper is the proposed design and evaluation of the dual-thread speculation system. this design point has very low complexity and reaps most of the gains of a system.

关键词： computer architecture thread-level speculation simultaneous multithreading chip multiprocessors thread-level parallelism

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Statistical performance Comparisons of computers

Statistical Performance Comparisons of Computers

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18th IEEE international symposium on high-performance computer architecture (HPCA)

作者： Chen, Tianshi Chen, Yunji Guo, Qi Temam, Olivier Wu, Yue Hu, Weiwu Chinese Acad Sci State Key Lab Comp Architecture Inst Comp Technol Beijing Peoples R China INRIA Saclay Orsay France Univ Pittsburgh Dept ECE Pittsburgh PA 15213 USA

ISBN: (纸本)9781467308243;9781467308267

As a fundamental task in computer architecture research, performance comparison has been continuously hampered by the variability of computer performance. In traditional performance comparisons, the impact of performance variability is usually ignored (i.e., the means of performance measurements are compared regardless of the variability), or in the few cases where it is factored in using parametric confidence techniques, the confidence is either erroneously computed based on the distribution of performance measurements (with the implicit assumption that it obeys the normal law), instead of the distribution of sample mean of performance measurements, or too few measurements are considered for the distribution of sample mean to be normal. We first illustrate how such erroneous practices can lead to incorrect comparisons. then, we propose a non-parametric Hierarchical performance Testing (HPT) framework for performance comparison, which is significantly more practical than standard parametric techniques because it does not require to collect a large number of measurements in order to achieve a normal distribution of the sample mean. this HPT framework has been implemented as an open-source software.

关键词： Sample mean computers performance metrics computer performance open source software HPT gene high pressure tests Gaussian distribution IMPACT PROPERTIES

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Network Congestion Avoidance through Speculative Reservation

Network Congestion Avoidance Through Speculative Reservation

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18th IEEE international symposium on high-performance computer architecture (HPCA)

作者： Jiang, Nan Becker, Daniel U. Michelogiannakis, George Dally, William J. Stanford Univ Stanford CA 94305 USA

ISBN: (纸本)9781467308243

Congestion caused by hot-spot traffic can significantly degrade the performance of a computer network. In this study, we present the Speculative Reservation Protocol (SRP), a new network congestion control mechanism that relieves the effect of hot-spot traffic in high bandwidth, low latency, lossless computer networks. Compared to existing congestion control approaches like Explicit Congestion Notification (ECN), which react to network congestion through packet marking and rate throttling, SRP takes a proactive approach of congestion avoidance. Using a light-weight endpoint reservation scheme and speculative packet transmission, SRP avoids hot-spot congestion while incurring minimal overhead. Our simulation results show that SRP responds more rapidly to the onset of severe hot-spots than ECN and has a higher network throughput on bursty network traffic. SRP also performs comparably to networks without congestion control on benign traffic patterns by reducing the latency and throughput overhead commonly associated with reservation protocols.

关键词： Network Congestion Signal Recognition Particle computer network Network throughput ECN (3beta,5alpha,17beta)-17-hydroxyestrane-3-carbonitrile Resource Reservation Protocol Hot spots congestion avoidance traffic patterns

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Pacman: Tolerating Asymmetric Data Races with Unintrusive Hardware

Pacman: Tolerating Asymmetric Data Races with Unintrusive Ha...

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18th IEEE international symposium on high-performance computer architecture (HPCA)

作者： Qi, Shanxiang Otsuki, Norimasa Nogueira, Lois Orosa Muzahid, Abdullah Torrellas, Josep Univ Illinois Urbana IL USA

ISBN: (纸本)9781467308243

Data races are a major contributor to parallel software unreliability. A type of race that is both common and typically harmful is the Asymmetric data race. It occurs when at least one of the racing threads is inside a critical section. Current proposals that target them are software-based. they slow down execution and require significant compiler, operating system (OS), or application changes. this paper proposes the first scheme to tolerate asymmetric data races in production runs with negligible execution overhead. the scheme, called Pacman, exploits cache coherence hardware to temporarily protect the variables that a thread accesses in a critical section from other threads' requests. Unlike previous schemes, Pacman induces negligible slowdown, needs no support from the compiler or (in the baseline design)from the OS, and requires no application source code changes. In addition, its hardware is relatively unintrusive. We test Pacman with the SPLASH-2, PARSEC, Sphinx3, and Apache codes, and discover two unreported asymmetric data races.

关键词： Racial Stocks critical zone computer hardware compilers thREADS Legal Executions osmium SLOWING-DOWN

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high performance computing Infrastructure in Technical University Research 18

High Performance Computing Infrastructure in Technical Unive...

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IEEE 18th international Conference on Intelligent computer Communication and Processing (ICCP)

作者： Gorgan, Dorian Tech Univ Cluj Napoca Dept Comp Sci Cluj Napoca Romania

ISBN: (纸本)9781665464376

A technical university needs high performance computing resources to support the research activity carried out by interdisciplinary teams, through heterogeneous, various and flexible configurations. the CloudUT infrastructure has been designed and developed to meet the requirements and performances necessary for research projects in the scientific and engineering fields specific to the Technical University of Cluj-Napoca such as big data, artificial intelligence, spatial data, satellite data, internet of things, complex simulation, and computer assisted design. this paper analysis and highlight the challenges and issues on finding efficient solutions for the distributed architecture, parallel computing, massive data, flexible architectures, virtualization, cloud applications and services for covering a large range of technical domains of engineering such as mechanics, automation and computers, civil and building services, electric, architecture and urban planning, electronics, robotics, and mechatronics.

关键词： high performance computation cloud infrastructure technical university research activity interdisciplinary research

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Best of SBAC-PAD 2012

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PARALLEL computing 2014年第9期40卷 512-513页

作者： Schnorr, Lucas Mello Alexandre Navaux, Philippe Olivier Univ Fed Rio Grande do Sul Inst Informat BR-91501970 Porto Alegre RS Brazil

this special issue presents new trends in computer architecture and in parallel and distributed systems. It is based on the best papers of the 24th international symposium on computer architecture and high performance computing, which was held in New York, NY, USA on October 24-26, 2012 in the Columbia University. the authors were invited to provide extended versions of the papers presented in the conference, taking into account suggestions by the double-blinded peer review process and comments gathered during the conference.

关键词： computer architecture Parallel and distributed systems high performance computing

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Computational Sprinting

Computational Sprinting

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18th IEEE international symposium on high-performance computer architecture (HPCA)

作者： Raghavan, Arun Luo, Yixin Chandawalla, Anuj Papaefthymiou, Marios Pipe, Kevin P. Wenisch, thomas F. Martin, Milo M. K. Univ Penn Dept Comp & Informat Sci Philadelphia PA 19104 USA Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI USA Univ Michigan Dept Mech Engn Ann Arbor MI USA

ISBN: (纸本)9781467308243;9781467308267

Although transistor density continues to increase, voltage scaling has stalled and thus power density is increasing each technology generation. Particularly in mobile devices, which have limited cooling options, these trends lead to a utilization wall in which sustained chip performance is limited primarily by power rather than area. However, many mobile applications do not demand sustained performance;rather they comprise short bursts of computation in response to sporadic user activity. To improve responsiveness for such applications, this paper explores activating otherwise powered-down cores for sub-second bursts of intense parallel computation. the approach exploits the concept of computational sprinting, in which a chip temporarily exceeds its sustainable thermal power budget to provide instantaneous throughput, after which the chip must return to nominal operation to cool down. To demonstrate the feasibility of this approach, we analyze the thermal and electrical characteristics of a smart-phone-like system that nominally operates a single core (similar to 1W peak), but can sprint with up to 16 cores for hundreds of milliseconds. We describe a thermal design that incorporates phase-change materials to provide thermal capacitance to enable such sprints. We analyze image recognition kernels to show that parallel sprinting has the potential to achieve the task response time of a 16W chip within the thermal constraints of a 1W mobile platform.

关键词： computer chips DNA Microarrays core thermal capacitance Phase change materials thermal design Mobile devices ELECTRICAL CHARACTERISTICS MILLISECOND thermal Energy sources Core samples Responsiveness Cooling

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high-level service connectors for component-based high performance computing

High-level service connectors for component-based high perfo...

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19th international symposium on computer architecture and high performance computing

作者： de Carvalho-Junior, Francisco Heron Correa, Ricardo Cordeiro Araujo, Gisele Azevedo Silva, Jefferson Carvalho Lins, Rafael Duelre Univ Fed Ceara Dept Comp Fortaleza Ceara Brazil Univ Fed Pernambuco Dept Elect Sistemas Recife PE Brazil

ISBN: (纸本)9780769530147

Component-based programming has been applied to address the requirements of applications in high performance computing (HPC). the usual service connectors of commercial component models do not fit some requirements of HPC, mainly regarding the support of parallelism, however this paper looks at extensions to the usual notion of service connector to meet such requirements, using the # component model as a substratum, evidencing its expressiveness.

关键词： computer programming

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