the proceedings contain 9 papers. the special focus in this conference is on logic-based methods and tools. the topics include: Using the tools of logicprogramming in the security industry;prolog visualization system...
the proceedings contain 9 papers. the special focus in this conference is on logic-based methods and tools. the topics include: Using the tools of logicprogramming in the security industry;prolog visualization system using logichart diagrams;a semantics-aware editing environment for prolog in eclipse;on the generation of test data for prolog by partial evaluation;improving size-change analysis in offline partial evaluation;a lightweight combination of semantics for non-deterministic functions;Rfuzzy framework;constraint solving for high-level WCET analysis and better termination for prolog withconstraints.
the safety of our day-to-day life depends crucially on the correct functioning of embedded software systems which control the functioning of more and more technical devices. Many of these software systems are time-cri...
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the safety of our day-to-day life depends crucially on the correct functioning of embedded software systems which control the functioning of more and more technical devices. Many of these software systems are time-critical. Hence, computations performed need not only to be correct, but must also be issued in a timely fashion. Worst case exe- cution time (WCET) analysis is concerned with computing tight upper bounds for the execution time of a system in order to provide formal guarantees for the proper timing behaviour of a system. Central for this is to compute safe and tight bounds for loops and recursion depths. In this paper, we highlight the TuBound approach to this challenge at whose heart is a constraintlogic based approach for loop analysis.
In recent work, we have proposed an approach to Test Data Generation (TDG) of imperative bytecode by partial evaluation (PE) of CLP which consists in two phases: (1) the bytecode program is first transformed into an e...
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In recent work, we have proposed an approach to Test Data Generation (TDG) of imperative bytecode by partial evaluation (PE) of CLP which consists in two phases: (1) the bytecode program is first transformed into an equivalent CLP program by means of interpretive compilation by PE, (2) a second PE is performed in order to supervise the generation of test-cases by execution of the CLP decompiled program. the main advantages of TDG by PE include flexibility to handle new coverage criteria, the possibility to obtain test-case generators and its simplicity to be implemented. the approach in principle can be directly applied for TDG of any imperative language. However, when one tries to apply it to a declarative language like Prolog, we have found as a main difficulty the generation of test-cases which cover the more complex control flow of Prolog. Essentially, the problem is that an intrinsic feature of PE is that it only computes non-failing derivations while in TDG for Prolog it is essential to generate test-cases associated to failing computations. Basically, we propose to transform the original Prolog program into an equivalent Prolog program with explicit failure by partially evaluating a Prolog interpreter which captures failing derivations w.r.t. the input program. Another issue that we discuss in the paper is that, while in the case of bytecode the underlying constraint domain only manipulates integers, in Prolog it should properly handle the symbolic data manipulated by the program. the resulting scheme is of interest for bringing the advantages which are inherent in TDG by PE to the field of logicprogramming.
A geometric programming framework is proposed in this paper to automate exploration of the design space consisting of data reuse (buffering) exploitation and loop-level parallelization, in the context of FPGA-targeted...
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ISBN:
(纸本)9781424419609
A geometric programming framework is proposed in this paper to automate exploration of the design space consisting of data reuse (buffering) exploitation and loop-level parallelization, in the context of FPGA-targeted hardware compilation. We expose the dependence between data reuse and data-level parallelization and explore both problems under the on-chip memory constraint for performance-optimal designs within a single optimization step. Results from applying this framework to several real benchmarks demonstrate that given different constraints on on-chip memory utilization, the corresponding performance-optimal designs are automatically determined by the framework, and performance improvements up to 4.7 times have been achieved compared withthe method that first explores data reuse and then performs parallelization.
this paper explores an approach to design for verification in systems built atop a middleware framework which separates synchronization concerns from the "core-functionallogic" of a program. the framework i...
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ISBN:
(纸本)9781627486606
this paper explores an approach to design for verification in systems built atop a middleware framework which separates synchronization concerns from the "core-functionallogic" of a program. the framework is based on a language-independent compositional model of synchronization contracts, called Szumo, which integrates well with popular OO design artifacts and provides strong guarantees of non-interference for a class of strictly exclusive systems. An approach for extracting models from Szumo design artifacts and analyzing the generated models to detect deadlocks is described. A key decision was to use constraint Handling Rules to express the semantics of synchronization contracts, which allowed a transparent model of the implementation logic.
this paper explores an approach to design for verification in systems built atop a middleware framework which separates synchronization concerns from the "core-functionallogic" of a program. the framework i...
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this paper explores an approach to design for verification in systems built atop a middleware framework which separates synchronization concerns from the "core-functionallogic" of a program. the framework is based on a language-independent compositional model of synchronization contracts, called Szumo, which integrates well with popular OO design artifacts and provides strong guarantees of non-interference for a class of strictly exclusive systems. An approach for extracting models from Szumo design artifacts and analyzing the generated models to detect deadlocks is described. A key decision was to use constraint Handling Rules to express the semantics of synchronization contracts, which allowed a transparent model of the implementation logic.
We propose to extend the algebraic-coalgebraic specification language COCASL by full coalgebraic modal logic based on predicate liftings for functors. this logic is more general than the modal logic previously used in...
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ISBN:
(纸本)9783540719977
We propose to extend the algebraic-coalgebraic specification language COCASL by full coalgebraic modal logic based on predicate liftings for functors. this logic is more general than the modal logic previously used in COCASL and supports the specification of a variety of modal logics, such as graded modal logic, majority logic, and probabilistic modal logic. COCASL thus becomes a modern modal language that covers a wide range of Kripke and non-Kripke semantics of modal logics via the coalgebraic interpretation.
SVtL is the core of a slicing-based verification environment for UML statechart models. We present an overview of the SVtL software architecture. Special attention is paid to the slicing approach. Slicing reduces the ...
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ISBN:
(纸本)9783540719977
SVtL is the core of a slicing-based verification environment for UML statechart models. We present an overview of the SVtL software architecture. Special attention is paid to the slicing approach. Slicing reduces the complexity of the verification approach, based on removing pieces of the model that are not of interest during verification. In [18] a slicing algorithm has been proposed for statecharts, but it was not able to handle orthogonal regions efficiently. We optimize this algorithm by removing false dependencies, relying on the broadcasting mechanism between different parts of the statechart model.
the theory of abstract algebraic logic aims at drawing a strong bridge between logic and universal algebra, namely by generalizing the well known connection between classical propositional logic and Boolean algebras. ...
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ISBN:
(纸本)9783540719977
the theory of abstract algebraic logic aims at drawing a strong bridge between logic and universal algebra, namely by generalizing the well known connection between classical propositional logic and Boolean algebras. Despite of its successfulness, the current scope of application of the theory is rather limited. Namely, logics with a many-sorted language simply fall out from its scope. Herein, we propose a way to extend the existing theory in order to deal also with many-sorted logics, by capitalizing on the theory of many-sorted equational logic. Besides showing that a number of relevant concepts and results extend to this generalized setting, we also analyze in detail the examples of first-order logic and the paraconsistent logic C-1 of da Costa.
We connect the algebraic specification language CASL with a variety of automated first-order provers. the heart of this connection is an institution comorphism from CASL to SoftFOL (softly typed firstorder logic);the ...
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ISBN:
(纸本)9783540719977
We connect the algebraic specification language CASL with a variety of automated first-order provers. the heart of this connection is an institution comorphism from CASL to SoftFOL (softly typed firstorder logic);the latter is then translated to the provers' input syntaxes. We also describe a GUI integrating the translations and the provers into the Heterogeneous Tool Set. We report on experiences with provers, which led to fine-tuning of the translations. this framework can also be used for checking consistency of specifications.
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