检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

36 篇 会议
1 册 图书

馆藏范围

36 篇 电子文献
1 种 纸本馆藏

日期分布

学科分类号

33 篇 工学
- 29 篇 软件工程
- 25 篇 计算机科学与技术...
- 2 篇 信息与通信工程
- 2 篇 控制科学与工程
- 2 篇 土木工程
- 1 篇 材料科学与工程（可...
- 1 篇 电气工程
- 1 篇 电子科学与技术（可...
5 篇 管理学
- 4 篇 图书情报与档案管...
- 2 篇 管理科学与工程(可...
- 1 篇 工商管理
2 篇 理学
- 2 篇 数学

主题

3 篇 object oriented ...
3 篇 performance
3 篇 design
3 篇 semantics
1 篇 low-locality
1 篇 dma
1 篇 heterogeneous me...
1 篇 flexible structu...
1 篇 structured progr...
1 篇 fast logging
1 篇 crash-consistent...
1 篇 operating system...
1 篇 b plus trees
1 篇 deterministic re...
1 篇 high level langu...
1 篇 computer archite...
1 篇 buffered writes
1 篇 fortran (program...
1 篇 indirect jumps
1 篇 virtual function...

机构

1 篇 ibm research cen...
1 篇 massachusetts in...
1 篇 coll william & m...
1 篇 computer science...
1 篇 univ calif san d...
1 篇 univ chinese aca...
1 篇 university of il...
1 篇 university of ca...
1 篇 princeton univ p...
1 篇 georgia inst tec...
1 篇 université de te...
1 篇 univ illinois ur...
1 篇 aws ai united st...
1 篇 department of co...
1 篇 at t belt labora...
1 篇 intermetrics inc...
1 篇 huawei technol p...
1 篇 information syst...
1 篇 schlumberger-dol...
1 篇 harvard universi...

作者

1 篇 liskov barbara
1 篇 kaufmann antoine
1 篇 lu maohua
1 篇 lecarme olivier
1 篇 sui xiufeng
1 篇 prenner charles ...
1 篇 chiueh tzi-cker
1 篇 sharma naveen kr...
1 篇 hoseinzadeh mort...
1 篇 kim hyesoon
1 篇 dinitz rick
1 篇 liu xu
1 篇 smith reid g.
1 篇 freiburghouse ro...
1 篇 morris james b.
1 篇 grossman dan
1 篇 ceze luis
1 篇 zaks rodnay
1 篇 hwu wen-mei
1 篇 song xiang

语言

36 篇 英文
1 篇 中文

检索条件"任意字段=1973 ACM SIGPLAN - SIGOPS Interface Meeting: Programming Languages - Operating Systems"

共 37 条记录，以下是1-10 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

ShakeFlow: Functional Hardware Description with Latency-Insensitive interface Combinators 2023

ShakeFlow: Functional Hardware Description with Latency-Inse...

引用

28th acm International Conference on Architectural Support for programming languages and operating systems (ASPLOS)

作者： Han, Sungsoo Jang, Minseong Kang, Jeehoon Korea Adv Inst Sci & Technol Daejeon South Korea

ISBN: (纸本)9781450399166

Functional programming's benefits for hardware description have long been recognized in the literature. In particular, functional hardware description languages provide combinators such as maps and filters to facilitate the compositional description of circuits. However, it is challenging to apply functional programming with combinators to complex circuits with latency-insensitive interfaces such as valid/ready interfaces due to the cyclic nature of their forward and backward ports. In this work, we present ShakeFlow: the first functional hardware description language supporting latency-insensitive interface combinators. ShakeFlow provides extensible support for custom interfaces and combinators and a compiler to synthesizable Verilog and FIRRTL. We port a part of the BaseJump STL library and the Corundum 100Gbps NIC from (System)Verilog to ShakeFlow, reducing the code size by 38% and 26%, respectively. By experimenting with Corundum, we demonstrate that ShakeFlow is capable of designing realistic circuits, and porting to ShakeFlow does not incur significant resource and performance overhead.

关键词： hardware description language latency insensitive interface functional programming combinator

来源：评论

学校读者我要写书评

暂无评论

Hector: An Efficient programming and Compilation Framework for Implementing Relational Graph Neural Networks in GPU Architectures 24

Hector: An Efficient Programming and Compilation Framework f...

引用

29th acm International Conference on Architectural Support for programming languages and operating systems, ASPLOS 2024

作者： Wu, Kun Hidayetoğlu, Mert Song, Xiang Huang, Sitao Zheng, Da Nisa, Israt Hwu, Wen-Mei University of Illinois Urbana-Champaign United States Stanford University United States AWS AI United States University of California Irvine United States Nvidia University of Illinois Urbana-Champaign United States

ISBN: (纸本)9798400703867

Relational graph neural networks (RGNNs) are graph neural networks with dedicated structures for modeling the different types of nodes and edges in heterogeneous graphs. While RGNNs have been increasingly adopted in many real-world applications due to their versatility and accuracy, they pose performance and system design challenges: inherent memory-intensive computation patterns, the gap between the programming interface and kernel APIs, and heavy programming effort required to optimize kernels caused by their coupling with data layout and heterogeneity. To systematically address these challenges, we propose Hector, a novel two-level intermediate representation and its code generator framework that (a) captures the key properties of RGNN models, and opportunities to reduce memory accesses in inter-operator scheduling and materialization, (b) generates code with flexible data access schemes to eliminate redundant data copies, and (c) decouples model semantics, data layout, and operators-specific optimizations from each other to reduce programming effort. By building on one general matrix multiply (GEMM) template and a node/edge traversal template, Hector achieves up to 9.9× speed-up in inference and 43.7× speed-up in training compared with the state-ofthe-art public systems on select models, RGCN, RGAT and HGT, when running heterogeneous graphs provided by Deep Graph Library (DGL) and Open Graph Benchmark (OGB). In addition, Hector does not trigger any out-of-memory (OOM) exception in these tests. We also propose linear operator reordering and compact materialization to further accelerate the system by up to 3.8×. As an indicator of the reduction of programming effort, Hector takes in 51 lines of code expressing the three models and generates a total of 8K lines of CUDA and C++ code. Through profiling, we found that higher memory efficiency allows Hector to accommodate larger input and therefore attain higher throughput in forward propagation, while backward propaga

关键词： Application programming interfaces (API)

来源：评论

学校读者我要写书评

暂无评论

Corundum: Statically-Enforced Persistent Memory Safety 21

Corundum: Statically-Enforced Persistent Memory Safety

引用

26th International Conference on Architectural Support for programming languages and operating systems (ASPLOS)

作者： Hoseinzadeh, Morteza Swanson, Steven Univ Calif San Diego San Diego CA 92103 USA

ISBN: (纸本)9781450383172

Fast, byte-addressable, persistent main memories (PM) make it possible to build complex data structures that can survive system failures. programming for PM is challenging, not least because it combines well-known programming challenges like locking, memory management, and pointer safety with novel PM-specific bug types. It also requires logging updates to PM to facilitate recovery after a crash. A misstep in any of these areas can corrupt data, leak resources, or prevent successful recovery after a crash. Existing PM libraries in a variety of languages - C, C++, Java, Go - simplify some of these problems, but they still require the programmer to learn (and flawlessly apply) complex rules to ensure correctness. Opportunities for data-destroying bugs abound. This paper presents Corundum, a Rust-based library with an idiomatic PM programming interface and leverages Rust's type system to statically avoid most common PM programming bugs. Corundum lets programmers develop persistent data structures using familiar Rust constructs and have confidence that they will be free of those bugs. We have implemented Corundum and found its performance to be as good as or better than Intel's widely-used PMDK library, HP's Atlas, Mnemosyne, and go-pmem.

关键词： non-volatile memory programming library static bug detection crash-consistent programming

来源：评论

学校读者我要写书评

暂无评论

High Performance Packet Processing with FlexNIC 16

High Performance Packet Processing with FlexNIC

引用

21st International Conference on Architectural Support for programming languages and operating systems

作者： Kaufmann, Antoine Peter, Simon Sharma, Naveen Kr. Anderson, Thomas Krishnamurthy, Arvind Univ Washington Seattle WA 98195 USA Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781450340915

The recent surge of network I/O performance has put enormous pressure on memory and software I/O processing subsystems. We argue that the primary reason for high memory and processing overheads is the inefficient use of these resources by current commodity network interface cards (NICs). We propose FlexNIC, a flexible network DMA interface that can be used by operating systems and applications alike to reduce packet processing overheads. FlexNIC allows services to install packet processing rules into the NIC, which then executes simple operations on packets while exchanging them with host memory. Thus, our proposal moves some of the packet processing traditionally done in software to the NIC, where it can be done flexibly and at high speed. We quantify the potential benefits of FlexNIC by emulating the proposed FlexNIC functionality with existing hardware or in software. We show that significant gains in application performance are possible, in terms of both latency and throughput, for several widely used applications, including a key-value store, a stream processing system, and an intrusion detection system.

关键词： Network interface Card DMA Flexible Network Processing Match-and-Action Processing

来源：评论

学校读者我要写书评

暂无评论

memif: Towards programming Heterogeneous Memory Asynchronously 16

<i>memif</i>: Towards Programming Heterogeneous Memory Async...

引用

21st International Conference on Architectural Support for programming languages and operating systems

作者： Lin, Felix Xiaozhu Liu, Xu Purdue ECE W Lafayette IN 47907 USA Coll William & Mary Williamsburg VA 23187 USA

ISBN: (纸本)9781450340915

To harness a heterogeneous memory hierarchy, it is advantageous to integrate application knowledge in guiding frequent memory move, i.e., replicating or migrating virtual memory regions. To this end, we present memif, a protected OS service for asynchronous, hardware-accelerated memory move. Compared to the state of the art - page migration in Linux, memif incurs low overhead and low latency;in order to do so, it not only redefines the semantics of kernel interface but also overhauls the underlying mechanisms, including request/completion management, race handling, and DMA engine configuration. We implement memif in Linux for a server-class system-on- chip that features heterogeneous memories. Compared to the current Linux page migration, memif reduces CPU usage by up to 15% for small pages and by up to 38x for large pages;in continuously serving requests, memif has no need for request batching and reduces latency by up to 63%. By crafting a small runtime atop memif, we improve the throughputs for a set of streaming workloads by up to 33%. Overall, memif has opened the door to software management of heterogeneous memory.

关键词： operating systems Heterogeneous Memory Data-intensive Computing

来源：评论

学校读者我要写书评

暂无评论

COATCheck: Verifying Memory Ordering at the Hardware-OS interface 16

COATCheck: Verifying Memory Ordering at the Hardware-OS Inte...

引用

21st International Conference on Architectural Support for programming languages and operating systems

作者： Lustig, Daniel Sethi, Geet Martonosi, Margaret Bhattacharjee, Abhishek Princeton Univ Princeton NJ 08544 USA Rutgers State Univ New Brunswick NJ USA

ISBN: (纸本)9781450340915

Modern computer systems include numerous compute elements, from CPUs to GPUs to accelerators. Harnessing their full potential requires well-defined, properly-implemented memory consistency models (MCMs), and low-level system functionality such as virtual memory and address translation (AT). Unfortunately, it is difficult to specify and implement hardware-OS interactions correctly;in the past, many hardware and OS specification mismatches have resulted in implementation bugs in commercial processors. In an effort to resolve this verification gap, this paper makes the following contributions. First, we present COATCheck(1), an address translation-aware framework for specifying and statically verifying memory ordering enforcement at the microarchitecture and operating system levels. We develop a domain-specific language for specifying ordering enforcement, for including ordering-related OS events and hardware micro-operations, and for programmatically enumerating happens-before graphs. Using a fast and automated static constraint solver, COATCheck can efficiently analyze interesting and important memory ordering scenarios for modern, high-performance, out-of-order processors. Second, we show that previous work on Virtual Address Memory Consistency (VAMC) does not capture every translation-related ordering scenario of interest, and that some such cases even fall outside the traditional scope of consistency. We therefore introduce the term transistency model to describe the superset of consistency which captures all translation-aware sets of ordering rules.

关键词： virtual memory verification computer architecture address translation memory consistency models

来源：评论

学校读者我要写书评

暂无评论

Supporting Differentiated Services in Computers via Programmable Architecture for Resourcing-on-Demand (PARD) 15

Supporting Differentiated Services in Computers via Programm...

引用

20th International Conference on Architectural Support for programming languages and operating systems (ASPLOS)

作者： Ma, Jiuyue Sui, Xiufeng Sun, Ninghui Li, Yupeng Yu, Zihao Huang, Bowen Xu, Tianni Yao, Zhicheng Chen, Yun Wang, Haibin Zhang, Lixin Bao, Yungang Chinese Acad Sci ICT State Key Lab Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China Huawei Technol Beijing Peoples R China

ISBN: (纸本)9781450328357

This paper presents PARD, a programmable architecture for resourcing-on-demand that provides a new programming interface to convey an application's high-level information like quality-of-service requirements to the hardware. PARD enables new functionalities like fully hardware-supported virtualization and differentiated services in computers. PARD is inspired by the observation that a computer is inherently a network in which hardware components communicate via packets (e.g., over the NoC or PCIe). We apply principles of software-defined networking to this intra-computer network and address three major challenges. First, to deal with the semantic gap between high-level applications and underlying hardware packets, PARD attaches a high-level semantic tag (e.g., a virtual machine or thread ID) to each memory-access, I/O, or interrupt packet. Second, to make hardware components more manageable, PARD implements programmable control planes that can be integrated into various shared resources (e.g., cache, DRAM, and I/O devices) and can differentially process packets according to tag-based rules. Third, to facilitate programming, PARD abstracts all control planes as a device file tree to provide a uniform programming interface via which users create and apply tag-based rules. Full-system simulation results show that by co-locating latency-critical memcached applications with other workloads PARD can improve a four-core computer's CPU utilization by up to a factor of four without significantly increasing tail latency. FPGA emulation based on a preliminary RTL implementation demonstrates that the cache control plane introduces no extra latency and that the memory control plane can reduce queueing delay for high-priority memory-access requests by up to a factor of 5.6.

关键词： Hardware/Software interface QoS Data Center

来源：评论

学校读者我要写书评

暂无评论

Low-level detection of language-level data races with LARD 14

Low-level detection of language-level data races with LARD

引用

19th International Conference on Architectural Support for programming languages and operating systems, ASPLOS 2014

作者： Wood, Benjamin P. Ceze, Luis Grossman, Dan University of Washington United States

ISBN: (纸本)9781450323055

Researchers have proposed always-on data-race exceptions as a way to avoid the ill effects of data races, but slow performance of accurate dynamic data-race detection remains a barrier to the adoption of always-on data-race exceptions. Proposals for accurate low-level (e.g., hardware) data-race detection have the potential to reduce this performance barrier. This paper explains why low-level data-race detectors are wrong for programs written in high-level languages (e.g., Java): they miss true data races and report false data races in these programs. To bring the benefits of low-level datarace detection to high-level languages, we design low-level abstractable race detection (LARD), an extension of the interface between low-level data-race detectors and run-time systems that enables accurate language-level data-race detection using low-level detection mechanisms. We implement accurate LARD data-race exception support for Java, coupling a modified Jikes RVM Java virtual machine and a simulated hardware race detector. We evaluate our detector's accuracy against an accurate dynamic Java data-race detector and other low-level race detectors without LARD, showing that näive accurate low-level data-race detectors suffer from many missed and false language-level races in practice, and that LARD prevents this inaccuracy. Copyright is held by the owner/author(s).

关键词： Java programming language

来源：评论

学校读者我要写书评

暂无评论

Iago Attacks: Why the System Call API is a Bad Untrusted RPC interface 13

Iago Attacks: Why the System Call API is a Bad Untrusted RPC...

引用

18th International Conference on Architectural Support for programming languages and operating systems

作者： Checkoway, Stephen Shacham, Hovav Johns Hopkins Univ Baltimore MD 21218 USA Univ Calif San Diego San Diego CA USA

ISBN: (纸本)9781450318709

In recent years, researchers have proposed systems for running trusted code on an untrusted operating system. Protection mechanisms deployed by such systems keep a malicious kernel from directly manipulating a trusted application's state. Under such systems, the application and kernel are, conceptually, peers, and the system call API defines an RPC interface between them. We introduce Iago attacks, attacks that a malicious kernel can mount in this model. We show how a carefully chosen sequence of integer return values to Linux system calls can lead a supposedly protected process to act against its interests, and even to undertake arbitrary computation at the malicious kernel's behest. Iago attacks are evidence that protecting applications from malicious kernels is more difficult than previously realized.

关键词： Security Iago attacks system call Overshadow

来源：评论

学校读者我要写书评

暂无评论

ASPLOS 2013 - 18th International Conference on Architectural Support for programming languages and operating systems

ASPLOS 2013 - 18th International Conference on Architectural...

引用

18th International Conference on Architectural Support for programming languages and operating systems, ASPLOS 2013

ISBN: (纸本)9781450318709

The proceedings contain 45 papers. The topics discussed include: cooperative empirical failure avoidance for multithreaded programs;parasol and GreenSwitch: managing datacenters powered by renewable energy;power containers: an OS facility for fine-grained power and energy management on multicore servers;ConAir: featherweight concurrency bug recovery via single-threaded idempotent execution;using likely invariants for automated software fault localization;the rise of the expert amateur: DIY culture and the evolution of computer science;DeAliaser: alias speculation using atomic region support;regularities considered harmful: forcing randomness to memory accesses to reduce row buffer conflicts for multi-core, multi-bank systems;a study of the scalability of stop-the-world garbage collectors on multicores;Iago attacks: why the system call API is a bad untrusted RPC interface;and InkTag: secure applications on an untrusted operating system.

关键词：

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共4页 << < 1 2 3 4 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：