检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

19 篇 会议

馆藏范围

19 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

16 篇 工学
- 16 篇 计算机科学与技术...
- 2 篇 电气工程
- 2 篇 软件工程
1 篇 理学
- 1 篇 数学

主题

6 篇 reconfigurable a...
5 篇 computer archite...
5 篇 hardware
4 篇 field programmab...
3 篇 parallel process...
3 篇 computational mo...
3 篇 kernel
2 篇 parallel archite...
2 篇 pixel
2 篇 embedded systems
2 篇 arrays
2 篇 multiprocessing ...
2 篇 fpga architectur...
2 篇 software
2 篇 multicore proces...
2 篇 fpga
2 篇 reconfigurable c...
1 篇 xilinx virtex-6 ...
1 篇 multicore reconf...
1 篇 biology computin...

机构

2 篇 karlsruhe inst t...
1 篇 politecn torino ...
1 篇 univ jaume 1 dep...
1 篇 institute of tel...
1 篇 univ so calif de...
1 篇 microsoft res ca...
1 篇 univ calif san d...
1 篇 steinbuch centre...
1 篇 the pennsylvania...
1 篇 univ illinois co...
1 篇 halmstad univ ct...
1 篇 univ politecn ca...
1 篇 mit comp sci & a...
1 篇 univ thessaly de...
1 篇 csic spanish nat...
1 篇 univ texas austi...
1 篇 city univ hong k...
1 篇 coppe sistemas a...
1 篇 department of co...
1 篇 univ toronto edw...

作者

1 篇 song dong
1 篇 arora manish
1 篇 pflucker otto
1 篇 chan ernie
1 篇 chan rosa h. m.
1 篇 christos d. anto...
1 篇 ahmed waheed
1 篇 cristal adrian
1 篇 li will x. y.
1 篇 goulding-hotta n...
1 篇 jens mittag
1 篇 hur ibrahim
1 篇 hulina paul t.
1 篇 unsal osman s.
1 篇 gong lingkan
1 篇 yang ziyu
1 篇 brown jeffery a.
1 篇 van de geijn rob...
1 篇 bauer lars
1 篇 taylor michael b...

语言

19 篇 英文

检索条件"任意字段=19th Annual Symposium on Parallelism in Algorithms and Architectures"

共 19 条记录，以下是1-10 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

SPAA'07: Proceedings of the Nineteenth annual symposium on parallelism in algorithms and architectures

SPAA'07: Proceedings of the Nineteenth Annual Symposium on P...

引用

SPAA'07: 19th annual symposium on parallelism in algorithms and architectures

ISBN: (纸本)159593667X

the proceedings contain 37 papers. the topics discussed include: on triangulation of simple networks;strong-diameter decompositions of minor free graphs;approximation algorithms for multiprocessor scheduling under uncertainty;scheduling DAGs on asynchronous processors;scheduling to minimize gaps and power consumption;cache-oblivious streaming B-trees;an experimental comparison of cache-oblivious and cache-conscious programs;scheduling threads for constructive cache sharing on CMPs;proximity-aware directory-based coherence for multi-core processor architectures;a parallel dynamic programming algorithm on a multi-core architecture;tight bounds for distributed selection;local MST computation with short advice;distributed approximation of capacitated dominating sets;packing to angles and sectors;and the notion of a timed register and its application to indulgent synchronization.

关键词： Computer programming

来源：评论

学校读者我要写书评

暂无评论

SuperMatrix Out-of-Order Scheduling of Matrix Operations for SMP and Multi-Core architectures 07

SuperMatrix Out-of-Order Scheduling of Matrix Operations for...

引用

19th annual symposium on parallelism in algorithms and architectures

作者： Chan, Ernie Quintana-Orti, Enrique S. Quintana-Orti, Gregorio van de Geijn, Robert Univ Texas Austin Dept Comp Sci Austin TX 78712 USA Univ Jaume 1 Dept Ingn & Ciencia Computad Castellon de La Plana Spain

ISBN: (纸本)9781595936677

We discuss the high-performance parallel implementation and execution of dense linear algebra matrix operations on SMP architectures;with an eye towards multi-core processors with many cores. We argue that traditional implementations, as those incorporated in LAPACK, cannot be easily modified to render high performance as well as scalability on these architectures. the solution we propose is to arrange the data structures and algorithms so that matrix blocks become the fundamental units of data;and operations on these blocks become the fundamental units of computation, resulting in algorithms-by-blocks as opposed to the snore traditional blocked algorithms. We show that this facilitates the adoption of techniques akin to dynamic scheduling and out-of-order execution usual in superscalar processors;which we name SuperMatrix Out-of-Order scheduling. Performance results on a 16 CPU Itanium2-based server are used to highlight opportunities and issues related to this new approach.

关键词： data affinity data-flow parallelism dense linear algebra libraries dynamic scheduling out-of-order execution

来源：评论

学校读者我要写书评

暂无评论

Synthesis of Platform architectures from OpenCL Programs

Synthesis of Platform Architectures from OpenCL Programs

引用

IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Owaida, Muhsen Bellas, Nikolaos Daloukas, Konstantis Antonopoulos, Christos D. Univ Thessaly Dept Comp & Commun Engn Volos Greece

ISBN: (纸本)9780769543017

the problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this paper, we use OpenCL, an industry supported standard for writing programs that execute on multicore platforms and accelerators such as GPUs. Our architectural synthesis tool, SOpenCL (Silicon-OpenCL), adapts OpenCL into a novel hardware design flow which efficiently maps coarse and fine-grained parallelism of an application onto an FPGA reconfigurable fabric. SOpenCL is based on a source-to-source code transformation step that coarsens the OpenCL fine-grained parallelism into a series of nested loops, and on a template-based hardware generation back-end that configures the accelerator based on the functionality and the application performance and area requirements. Our experimentation with a variety of OpenCL and C kernel benchmarks reveals that area, throughput and frequency optimized hardware implementations are attainable using SOpenCL.

关键词： Multithreading OpenCL Electronic Design Automation Reconfigurable Computing Embedded Systems FPGA

来源：评论

学校读者我要写书评

暂无评论

Proximity-Aware Directory-based Coherence for Multi-core Processor architectures 07

Proximity-Aware Directory-based Coherence for Multi-core Pro...

引用

19th annual symposium on parallelism in algorithms and architectures

作者： Brown, Jeffery A. Kumar, Rakesh Tullsen, Dean Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA Univ Illinois Coordinated Sci Lab Urbana IL 61801 USA

ISBN: (纸本)9781595936677

As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue for multi-core performance. this is exacerbated by the fact that interconnection speeds are not scaling well with technology. this paper describes mechanisms to accelerate coherence for a multi-core architecture that has multiple private L2 caches and a scalable point-to-point interconnect between cores. these techniques exploit the differences in geometry between chip multiprocessors and traditional multiprocessor architectures. Directory-based protocols have been proposed as a scalable alternative to snoop-based protocols. In this paper, we discuss implementations of coherence for CMPs and propose and evaluate a novel directory-based coherence scheme to improve the performance of parallel programs on such processors. Proximity-aware coherence accelerates read and write misses by initiating cache-to-cache transfers from the spatially closest sharer. this has the dual benefit of eliminating unnecessary accesses to off-Chip memory, and minimizing the distance over which communicated data moves across the network. the proposed schemes result in speedups up to 74.9% for our workloads.

关键词： Chip Multiprocessors Coherence

来源：评论

学校读者我要写书评

暂无评论

Programming Real-time Autofocus on a Massively Parallel Reconfigurable Architecture using Occam-pi

Programming Real-time Autofocus on a Massively Parallel Reco...

引用

IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Zain-ul-Abdin Ahlander, Anders Svensson, Bertil Halmstad Univ Ctr Res Embedded Syst Halmstad Sweden Saab Grp Business Area Elect Def Syst Gothenburg Sweden

ISBN: (纸本)9780769543017

Recently we proposed occam-pi as a high-level language for programming massively parallel reconfigurable architectures. the design of occam-pi incorporates ideas from CSP and pi-calculus to facilitate expressing parallelism and reconfigurability. the feasability of this approach was illustrated by building three occam-pi implementations of DCT executing on an Ambric. However, because DCT is a simple and well-studied algorithm it remained uncertain whether occam-pi would also be effective for programming novel, more complex algorithms. In this paper, we demonstrate the applicability of occam-pi for expressing various degrees of parallelism by implementing a significantly large case-study of focus criterion calculation in an autofocus algorithm on the Ambric architecture. Autofocus is a key component of synthetic aperture radar systems. Two implementations of focus criterion calculation were developed and evaluated on the basis of performance. the comparison of the performance results with a single threaded software implementation of the same algorithm show that the throughput of the two implementations are 11x and 23x higher than the sequential implementation despite a much lower (9x) clock frequency. the two designs are, respectively, 29x and 40x more energy efficient.

关键词： Ambric architecture CSP Computer architecture Concurrent programming models DCT Hardware Interpolation Mobile communication Parallel processing Pixel Reconfigurable Arcitectures Semantics high level languages high-level language massively parallel reconfigurable architecture occam-pi parallel architectures pi-calculus real-time autofocus reconfigurable architectures single threaded software implementation synthetic aperture radar systems

来源：评论

学校读者我要写书评

暂无评论

Parallel Suffix Array Construction for Shared Memory architectures

Parallel Suffix Array Construction for Shared Memory Archite...

引用

19th International symposium on String Processing and Information Retrieval (SPIRE) / 8th Latin American Web Congress (LA-WEB)

作者： Osipov, Vitaly Karlsruhe Inst Technol Karlsruhe Germany

ISBN: (纸本)9783642341083;9783642341090

We present the design of the algorithm for constructing the suffix array of a string using manycore GPUs. Despite of the wide usage in text processing and extensive research over two decades there was a lack of efficient algorithms that were able to exploit shared memory parallelism (as multicore CPUs as manycore GPUs) in practice. To the best of our knowledge we developed the first approach exposing shared memory parallelism that significantly outperforms the state-of-the-art existing implementations for sufficiently large inputs. We reduced the suffix array construction problem to a number of parallel primitives such as prefix-sum, radix sorting, random gather and scatter from/to the memory. thus, the performance of the algorithm merely depends on the performance of these primitives on the particular shared memory architecture. We demonstrate its performance on manycore GPUs, but the method can also be applied for other parallel architectures, such as multicores, CELL or Intel MIC.

关键词： Text processing

来源：评论

学校读者我要写书评

暂无评论

19th International symposium on Computer Architecture

19th International Symposium on Computer Architecture

引用

19th International symposium on Computer Architecture

ISBN: (纸本)0897915097

the following topics are dealt with: consistency for shared-memory multiprocessors;instruction-level parallelism;multiprocessor architectures;processor elements;multithreading;multithreaded architectures;message routing networks;I/O systems;program performance;vectors and streams;and system performance. Abstracts of individual papers can be found under the relevant classification codes in this or other issues.

关键词： Computer architecture

来源：评论

学校读者我要写书评

暂无评论

Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems

Reducing the Energy Cost of Irregular Code Bases in Soft Pro...

引用

IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Arora, Manish Sampson, Jack Goulding-Hotta, Nathan Babb, Jonathan Venkatesh, Ganesh Taylor, Michael Bedford Swanson, Steven Univ Calif San Diego Dept Comp Sci & Engn San Diego CA 92103 USA MIT Comp Sci & Artificial Intelligence Lab Cambridge MA 02139 USA

ISBN: (纸本)9780769543017

this paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide range of unmodified C programs. FPGAs are increasingly used to build large-scale systems, and many large software systems contain relatively little code that is amenable to automatic, semi-automatic, or even manual parallelization. Whereas accelerator approaches have traditionally achieved energy benefits as a side effect from increasing performance via parallel execution, ICERs aim to achieve energy gains even on code with little exploitable parallelism. Traditional approaches to automatically generating accelerators from existing software rely on inferring parallel execution from serial code, so they face the same code analysis challenges as parallelizing compilers. In contrast, because the ICER approach targets energy rather than performance, it easily scales to large, irregular applications that are poor candidates for traditional acceleration. Our results show that, compared to a baseline system with soft processor cores, ICERs can reduce energy consumption by up to 9.5x for the code they target and 2.8x for whole applications.

关键词： Accelerator architectures Reconfigurable architectures Energy efficiency High level synthesis

来源：评论

学校读者我要写书评

暂无评论

Memory latency effects in decoupled architectures with a single data memory module 92

Memory latency effects in decoupled architectures with a sin...

引用

19th International symposium on Computer Architecture

作者： Kurian, Lizyamma Hulina, Paul T. Coraor, Lee D. The Pennsylvania State Univ Univ Park United States

ISBN: (纸本)0897915097

Decoupled computer architectures, which partition the memory access and execute functions in a computer program and achieve high performance by exploiting the fine-grain parallelism between the two, are considered. A simulation study of the latency effects in decoupled computers when they are connected to a single, conventional, noninterleaved data memory module, so that the effect of decoupling is isolated from the improvement caused by the interleaving, is reported. the performance is compared to that of single processors with caches, the memory latency sensitivity of the decoupled systems is studied, and simulations are performed to determine the significance of data caches in a decoupled computer architecture.

关键词： Computer architecture

来源：评论

学校读者我要写书评

暂无评论

Reconsideration of Computing Paradigms and a Novel Reconfigurable Architecture

Reconsideration of Computing Paradigms and a Novel Reconfigu...

引用

IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Yan, Ming Yang, Ziyu Li, Sikun Yang, Liu Natl Univ Def Technol Sch Comp Changsha Hunan Peoples R China Hunan Univ Coll Comp & Commun Changsha Hunan Peoples R China

ISBN: (纸本)9780769543017

With the on-chip resources largely increased, the computing paradigm of modern architectures are much different from traditional ones. the relation between temporal computing and spatial computing is getting more and more intricate. In this paper, a coarse-grained reconfigurable architecture is proposed named as programmable dataflow computing architecture: ProDFA. With both fine-grained control ability and long-term control logic, ProDFA implements coarse-grained reconfigurability and fine-grained controllability, which brought both flexible programmability and high efficiency. A case study on block ciphers is done. A specific reconfigurable structure for block ciphers is designed and several mainstream block ciphers are mapped and evaluated. the experimental results show the high efficiency of the specific reconfigurable structure.

关键词： Arrays Clocks Computers Educational institutions ProDFA architecture Process control System-on-a-chip block cipher coarse-grained reconflgurable architecture computing paradigm controllability cryptography data flow computing fine-grained controllability flexible programmability long-term control logic on-chip resource programmable dataflow computing architecture reconfigurable architectures spatial computing temporal computing temporal logic

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共2页 << < 1 2 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：