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Advances in Molecular Quantum Computing: from Technological Modeling to Circuit Design 19

Advances in Molecular Quantum Computing: from Technological ...

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19th IEEE-Computer-Society annual symposium on VLSI (ISVLSI)

作者： Cirillo, Giovanni Amedeo Turvani, Giovanna Simoni, Mario Graziano, Mariagrazia Politecn Torino Dept Elect & Telecommun I-10129 Turin Italy Politecn Torino Dept Appl Sci & Technol I-10129 Turin Italy

ISBN: (纸本)9781728157757

Molecules are serious candidates for building hardware for quantum computers. they can encode quantum information onto electron or nuclear spins and some of them show important features as the scalability of the number of qubits and a universal set of quantum gates. In this paper we present our advances in the development of a classical simulation infrastructure for molecular Quantum Computing: starting from the definition of simplified models taking into account the main physical features of each analyzed molecule, quantum gates are defined over these models, thus permitting to take into account the real behavior of each technology during the simulation. An interface with a hardware-agnostic description language has been also developed. the knowledge of the behavior of real systems permits to optimize the design of quantum circuits at both physical and compilation levels. Elementary quantum algorithms have been simulated on three different molecular technologies by changing the physical parameters of polarization and manipulation and quantum circuit design strategies. Results confirm the dependency of the fidelity of the results on both levels, thus proving that the choice of optimal operating points and circuit optimization techniques as virtual-Z gates are fundamental for ensuring the execution of quantum circuits with negligible errors.

关键词： Molecular quantum computing molecular nanomagnets quantum computing architectures innovative technology

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Parallel Suffix Array Construction for Shared Memory architectures

Parallel Suffix Array Construction for Shared Memory Archite...

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19th International symposium on String Processing and Information Retrieval (SPIRE) / 8th Latin American Web Congress (LA-WEB)

作者： Osipov, Vitaly Karlsruhe Inst Technol Karlsruhe Germany

ISBN: (纸本)9783642341083;9783642341090

We present the design of the algorithm for constructing the suffix array of a string using manycore GPUs. Despite of the wide usage in text processing and extensive research over two decades there was a lack of efficient algorithms that were able to exploit shared memory parallelism (as multicore CPUs as manycore GPUs) in practice. To the best of our knowledge we developed the first approach exposing shared memory parallelism that significantly outperforms the state-of-the-art existing implementations for sufficiently large inputs. We reduced the suffix array construction problem to a number of parallel primitives such as prefix-sum, radix sorting, random gather and scatter from/to the memory. thus, the performance of the algorithm merely depends on the performance of these primitives on the particular shared memory architecture. We demonstrate its performance on manycore GPUs, but the method can also be applied for other parallel architectures, such as multicores, CELL or Intel MIC.

关键词： Text processing

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Synthesis of Platform architectures from OpenCL Programs

Synthesis of Platform Architectures from OpenCL Programs

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IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Owaida, Muhsen Bellas, Nikolaos Daloukas, Konstantis Antonopoulos, Christos D. Univ Thessaly Dept Comp & Commun Engn Volos Greece

ISBN: (纸本)9780769543017

the problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this paper, we use OpenCL, an industry supported standard for writing programs that execute on multicore platforms and accelerators such as GPUs. Our architectural synthesis tool, SOpenCL (Silicon-OpenCL), adapts OpenCL into a novel hardware design flow which efficiently maps coarse and fine-grained parallelism of an application onto an FPGA reconfigurable fabric. SOpenCL is based on a source-to-source code transformation step that coarsens the OpenCL fine-grained parallelism into a series of nested loops, and on a template-based hardware generation back-end that configures the accelerator based on the functionality and the application performance and area requirements. Our experimentation with a variety of OpenCL and C kernel benchmarks reveals that area, throughput and frequency optimized hardware implementations are attainable using SOpenCL.

关键词： Multithreading OpenCL Electronic Design Automation Reconfigurable Computing Embedded Systems FPGA

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Programming Real-time Autofocus on a Massively Parallel Reconfigurable Architecture using Occam-pi

Programming Real-time Autofocus on a Massively Parallel Reco...

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IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Zain-ul-Abdin Ahlander, Anders Svensson, Bertil Halmstad Univ Ctr Res Embedded Syst Halmstad Sweden Saab Grp Business Area Elect Def Syst Gothenburg Sweden

ISBN: (纸本)9780769543017

Recently we proposed occam-pi as a high-level language for programming massively parallel reconfigurable architectures. the design of occam-pi incorporates ideas from CSP and pi-calculus to facilitate expressing parallelism and reconfigurability. the feasability of this approach was illustrated by building three occam-pi implementations of DCT executing on an Ambric. However, because DCT is a simple and well-studied algorithm it remained uncertain whether occam-pi would also be effective for programming novel, more complex algorithms. In this paper, we demonstrate the applicability of occam-pi for expressing various degrees of parallelism by implementing a significantly large case-study of focus criterion calculation in an autofocus algorithm on the Ambric architecture. Autofocus is a key component of synthetic aperture radar systems. Two implementations of focus criterion calculation were developed and evaluated on the basis of performance. the comparison of the performance results with a single threaded software implementation of the same algorithm show that the throughput of the two implementations are 11x and 23x higher than the sequential implementation despite a much lower (9x) clock frequency. the two designs are, respectively, 29x and 40x more energy efficient.

关键词： Ambric architecture CSP Computer architecture Concurrent programming models DCT Hardware Interpolation Mobile communication Parallel processing Pixel Reconfigurable Arcitectures Semantics high level languages high-level language massively parallel reconfigurable architecture occam-pi parallel architectures pi-calculus real-time autofocus reconfigurable architectures single threaded software implementation synthetic aperture radar systems

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Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems

Reducing the Energy Cost of Irregular Code Bases in Soft Pro...

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IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Arora, Manish Sampson, Jack Goulding-Hotta, Nathan Babb, Jonathan Venkatesh, Ganesh Taylor, Michael Bedford Swanson, Steven Univ Calif San Diego Dept Comp Sci & Engn San Diego CA 92103 USA MIT Comp Sci & Artificial Intelligence Lab Cambridge MA 02139 USA

ISBN: (纸本)9780769543017

this paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide range of unmodified C programs. FPGAs are increasingly used to build large-scale systems, and many large software systems contain relatively little code that is amenable to automatic, semi-automatic, or even manual parallelization. Whereas accelerator approaches have traditionally achieved energy benefits as a side effect from increasing performance via parallel execution, ICERs aim to achieve energy gains even on code with little exploitable parallelism. Traditional approaches to automatically generating accelerators from existing software rely on inferring parallel execution from serial code, so they face the same code analysis challenges as parallelizing compilers. In contrast, because the ICER approach targets energy rather than performance, it easily scales to large, irregular applications that are poor candidates for traditional acceleration. Our results show that, compared to a baseline system with soft processor cores, ICERs can reduce energy consumption by up to 9.5x for the code they target and 2.8x for whole applications.

关键词： Accelerator architectures Reconfigurable architectures Energy efficiency High level synthesis

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Reconsideration of Computing Paradigms and a Novel Reconfigurable Architecture

Reconsideration of Computing Paradigms and a Novel Reconfigu...

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IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Yan, Ming Yang, Ziyu Li, Sikun Yang, Liu Natl Univ Def Technol Sch Comp Changsha Hunan Peoples R China Hunan Univ Coll Comp & Commun Changsha Hunan Peoples R China

ISBN: (纸本)9780769543017

With the on-chip resources largely increased, the computing paradigm of modern architectures are much different from traditional ones. the relation between temporal computing and spatial computing is getting more and more intricate. In this paper, a coarse-grained reconfigurable architecture is proposed named as programmable dataflow computing architecture: ProDFA. With both fine-grained control ability and long-term control logic, ProDFA implements coarse-grained reconfigurability and fine-grained controllability, which brought both flexible programmability and high efficiency. A case study on block ciphers is done. A specific reconfigurable structure for block ciphers is designed and several mainstream block ciphers are mapped and evaluated. the experimental results show the high efficiency of the specific reconfigurable structure.

关键词： Arrays Clocks Computers Educational institutions ProDFA architecture Process control System-on-a-chip block cipher coarse-grained reconflgurable architecture computing paradigm controllability cryptography data flow computing fine-grained controllability flexible programmability long-term control logic on-chip resource programmable dataflow computing architecture reconfigurable architectures spatial computing temporal computing temporal logic

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Towards Synthesis-Free JIT Compilation to Commodity FPGAs

Towards Synthesis-Free JIT Compilation to Commodity FPGAs

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IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Capalija, Davor Abdelrahman, Tarek S. Univ Toronto Edward S Rogers Sr Dept Elect & Comp Engn Toronto ON M4X 1K9 Canada

ISBN: (纸本)9780769543017

We explore the feasibility of accelerating soft processors by dynamically translating hot segments of code into FPGA circuits. We propose an approach that tackles two key challenges: the prohibitive compile time of standard synthesis tools and the limited run-time reconfigurability of commodity FPGAs. We use traces, or hot straight-line segments of code, as the units of code to translate into FPGA circuits, combined with a pre-synthesized overlay that is tuned for traces. the overlay, referred to as the Virtual Dynamically Reconfigurable (VDR) overlay consists of an array of functional units that are interconnected by a set of programmable switches. the overlay can be rapidly configured by the soft processor at run-time. Our approach avoids traditional synthesis and reduces code-to-circuit translation to the significantly faster mapping of instructions to VDR units. Preliminary evaluation shows that the overlay speeds up the execution of the benchmark by up to 9X over a Nios II processor. the overlay incurs a 6.4X penalty in resources compared to Nios II.

关键词： Dynamic acceleration of soft processors just-in-time compilation overlay architectures

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Modeling Dynamically Reconfigurable Systems for Simulation-based Functional Verification

Modeling Dynamically Reconfigurable Systems for Simulation-b...

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IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Gong, Lingkan Diessel, Oliver Univ New S Wales Sch Comp Sci & Engn Sydney NSW 2052 Australia

ISBN: (纸本)9780769543017

Dynamically Reconfigurable Systems (DRS), which allow logic to be partially reconfigured during run-time, are promising candidates for embedded and high-performance systems. However, their architectural flexibility introduces a new dimension to the functional verification problem. Dynamic reconfiguration requires the designer to consider new issues such as synchronizing, isolating and initializing reconfigurable modules. Furthermore, by exposing the FPGA architecture to the application specification, it has made functional verification dependent on the physical implementation. this paper studies simulation as the most fundamental approach to the functional verification of DRS. the main contribution of this paper is in proposing a verification-driven top-down modeling methodology that guides designers in refining their reconfigurable system design from the behavioral level to the register transfer level. We assess the feasibility of our methodology via a case study involving the design of a generic partial reconfiguration platform.

关键词： Computational modeling Computer bugs Data models Dynamically Reconfigurable Systems FPGA FPGA architecture Field programmable gate arrays Functional Verification Hardware design languages Kernel Libraries Top-down modeling methodology application specification dynamically reconfigurable systems embedded system embedded systems formal specification formal verification high-performance system reconfigurable architectures register transfer level simulation-based functional verification verification-driven top-down modeling methodology

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Run-Time Resource Allocation for Simultaneous Multi-Tasking in Multi-Core Reconfigurable Processors

Run-Time Resource Allocation for Simultaneous Multi-Tasking ...

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IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Ahmed, Waheed Shafique, Muhammad Bauer, Lars Hammerich, Manuel Henkel, Joerg Becker, Juergen Karlsruhe Inst Technol Karlsruhe Germany

ISBN: (纸本)9780769543017

State-of-the-art multi-core reconfigurable processors do not exploit the full potential of simultaneous multi-tasking with run-time adaptive reconfigurable fabric allocation. We propose a novel run-time system for simultaneous multi-tasking in a multi-core reconfigurable processor that adaptively allocates the mixed-grained reconfigurable fabric resource at run time among different tasks considering their performance constraints. Our scheme employs the novel concept of refined task-criticality (based on the functional-block-level performance constraints) considering the computational properties of dependent tasks and their inherent potential for acceleration. Our scheme dynamically compensates the deadline misses at the functional block level. It thereby reduces the potential task-level deadline misses under competing scenarios. With the help of a secure video conferencing application (with 4 dependent tasks of diverse computational properties), we demonstrate that our scheme reduces the deadline misses by (on average) 6x under given performance constraints, when compared to state-of-the-art reconfigurable processors [1, 9, 12].

关键词： Decoding Fabrics Kernel Multicore processing Program processors Quality of service Resource management adaptive reconfigurable fabric allocation functional-block-level performance constraint microprocessor chips mixed-grained reconfigurable fabric resource multicore reconfigurable processor multiprocessing systems reconfigurable architectures run-time resource allocation simultaneous multitasking task-criticality video conferencing

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TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System

TMbox: A Flexible and Reconfigurable 16-core Hybrid Transact...

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IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Sonmez, Nehir Arcas, Oriol Pflucker, Otto Unsal, Osman S. Cristal, Adrian Hur, Ibrahim Singh, Satnam Valero, Mateo Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna E-08028 Barcelona Spain CSIC Spanish Natl Res Council Madrid Spain Microsoft Res Cambridge Cambridge England

ISBN: (纸本)9780769543017

In this paper we present the design and implementation of TMbox: An MPSoC built to explore trade-offs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core Hybrid Transactional Memory implementation based on the TinySTM-ASF proposal on a Virtex-5 FPGA and we accelerate three benchmarks written to investigate TM.

关键词： Field programmable gate arrays Hardware MIPS R3000-compatible core MPSoC Multicore processing Proposals Registers Software TMbox TinySTM-ASF Virtex-5 FPGA electronic engineering computing field programmable gate arrays flexible 16-core hybrid transactional memory system flexible system logic design multicore design space multicore prototyping multiprocessing systems parallel programming parallel programming reconfigurable 16-core hybrid transactional memory system reconfigurable architectures reconfigurable computing system-on-chip transactional memory

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