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Towards Synthesis-Free JIT Compilation to Commodity FPGAs

Towards Synthesis-Free JIT Compilation to Commodity FPGAs

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IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Capalija, Davor Abdelrahman, Tarek S. Univ Toronto Edward S Rogers Sr Dept Elect & Comp Engn Toronto ON M4X 1K9 Canada

ISBN: (纸本)9780769543017

We explore the feasibility of accelerating soft processors by dynamically translating hot segments of code into FPGA circuits. We propose an approach that tackles two key challenges: the prohibitive compile time of standard synthesis tools and the limited run-time reconfigurability of commodity FPGAs. We use traces, or hot straight-line segments of code, as the units of code to translate into FPGA circuits, combined with a pre-synthesized overlay that is tuned for traces. the overlay, referred to as the Virtual Dynamically Reconfigurable (VDR) overlay consists of an array of functional units that are interconnected by a set of programmable switches. the overlay can be rapidly configured by the soft processor at run-time. Our approach avoids traditional synthesis and reduces code-to-circuit translation to the significantly faster mapping of instructions to VDR units. Preliminary evaluation shows that the overlay speeds up the execution of the benchmark by up to 9X over a Nios II processor. the overlay incurs a 6.4X penalty in resources compared to Nios II.

关键词： Dynamic acceleration of soft processors just-in-time compilation overlay architectures

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Modeling Dynamically Reconfigurable Systems for Simulation-based Functional Verification

Modeling Dynamically Reconfigurable Systems for Simulation-b...

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IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Gong, Lingkan Diessel, Oliver Univ New S Wales Sch Comp Sci & Engn Sydney NSW 2052 Australia

ISBN: (纸本)9780769543017

Dynamically Reconfigurable Systems (DRS), which allow logic to be partially reconfigured during run-time, are promising candidates for embedded and high-performance systems. However, their architectural flexibility introduces a new dimension to the functional verification problem. Dynamic reconfiguration requires the designer to consider new issues such as synchronizing, isolating and initializing reconfigurable modules. Furthermore, by exposing the FPGA architecture to the application specification, it has made functional verification dependent on the physical implementation. this paper studies simulation as the most fundamental approach to the functional verification of DRS. the main contribution of this paper is in proposing a verification-driven top-down modeling methodology that guides designers in refining their reconfigurable system design from the behavioral level to the register transfer level. We assess the feasibility of our methodology via a case study involving the design of a generic partial reconfiguration platform.

关键词： Computational modeling Computer bugs Data models Dynamically Reconfigurable Systems FPGA FPGA architecture Field programmable gate arrays Functional Verification Hardware design languages Kernel Libraries Top-down modeling methodology application specification dynamically reconfigurable systems embedded system embedded systems formal specification formal verification high-performance system reconfigurable architectures register transfer level simulation-based functional verification verification-driven top-down modeling methodology

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Run-Time Resource Allocation for Simultaneous Multi-Tasking in Multi-Core Reconfigurable Processors

Run-Time Resource Allocation for Simultaneous Multi-Tasking ...

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IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Ahmed, Waheed Shafique, Muhammad Bauer, Lars Hammerich, Manuel Henkel, Joerg Becker, Juergen Karlsruhe Inst Technol Karlsruhe Germany

ISBN: (纸本)9780769543017

State-of-the-art multi-core reconfigurable processors do not exploit the full potential of simultaneous multi-tasking with run-time adaptive reconfigurable fabric allocation. We propose a novel run-time system for simultaneous multi-tasking in a multi-core reconfigurable processor that adaptively allocates the mixed-grained reconfigurable fabric resource at run time among different tasks considering their performance constraints. Our scheme employs the novel concept of refined task-criticality (based on the functional-block-level performance constraints) considering the computational properties of dependent tasks and their inherent potential for acceleration. Our scheme dynamically compensates the deadline misses at the functional block level. It thereby reduces the potential task-level deadline misses under competing scenarios. With the help of a secure video conferencing application (with 4 dependent tasks of diverse computational properties), we demonstrate that our scheme reduces the deadline misses by (on average) 6x under given performance constraints, when compared to state-of-the-art reconfigurable processors [1, 9, 12].

关键词： Decoding Fabrics Kernel Multicore processing Program processors Quality of service Resource management adaptive reconfigurable fabric allocation functional-block-level performance constraint microprocessor chips mixed-grained reconfigurable fabric resource multicore reconfigurable processor multiprocessing systems reconfigurable architectures run-time resource allocation simultaneous multitasking task-criticality video conferencing

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Advances in Molecular Quantum Computing: from Technological Modeling to Circuit Design 19

Advances in Molecular Quantum Computing: from Technological ...

引用

19th IEEE-Computer-Society annual symposium on VLSI (ISVLSI)

作者： Cirillo, Giovanni Amedeo Turvani, Giovanna Simoni, Mario Graziano, Mariagrazia Politecn Torino Dept Elect & Telecommun I-10129 Turin Italy Politecn Torino Dept Appl Sci & Technol I-10129 Turin Italy

ISBN: (纸本)9781728157757

Molecules are serious candidates for building hardware for quantum computers. they can encode quantum information onto electron or nuclear spins and some of them show important features as the scalability of the number of qubits and a universal set of quantum gates. In this paper we present our advances in the development of a classical simulation infrastructure for molecular Quantum Computing: starting from the definition of simplified models taking into account the main physical features of each analyzed molecule, quantum gates are defined over these models, thus permitting to take into account the real behavior of each technology during the simulation. An interface with a hardware-agnostic description language has been also developed. the knowledge of the behavior of real systems permits to optimize the design of quantum circuits at both physical and compilation levels. Elementary quantum algorithms have been simulated on three different molecular technologies by changing the physical parameters of polarization and manipulation and quantum circuit design strategies. Results confirm the dependency of the fidelity of the results on both levels, thus proving that the choice of optimal operating points and circuit optimization techniques as virtual-Z gates are fundamental for ensuring the execution of quantum circuits with negligible errors.

关键词： Molecular quantum computing molecular nanomagnets quantum computing architectures innovative technology

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TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System

TMbox: A Flexible and Reconfigurable 16-core Hybrid Transact...

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IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Sonmez, Nehir Arcas, Oriol Pflucker, Otto Unsal, Osman S. Cristal, Adrian Hur, Ibrahim Singh, Satnam Valero, Mateo Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna E-08028 Barcelona Spain CSIC Spanish Natl Res Council Madrid Spain Microsoft Res Cambridge Cambridge England

ISBN: (纸本)9780769543017

In this paper we present the design and implementation of TMbox: An MPSoC built to explore trade-offs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core Hybrid Transactional Memory implementation based on the TinySTM-ASF proposal on a Virtex-5 FPGA and we accelerate three benchmarks written to investigate TM.

关键词： Field programmable gate arrays Hardware MIPS R3000-compatible core MPSoC Multicore processing Proposals Registers Software TMbox TinySTM-ASF Virtex-5 FPGA electronic engineering computing field programmable gate arrays flexible 16-core hybrid transactional memory system flexible system logic design multicore design space multicore prototyping multiprocessing systems parallel programming parallel programming reconfigurable 16-core hybrid transactional memory system reconfigurable architectures reconfigurable computing system-on-chip transactional memory

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FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking Activities

FPGA Architecture of Generalized Laguerre-Volterra MIMO Mode...

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IEEE 19th annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Li, Will X. Y. Cheung, Ray C. C. Zhang, Wei Chan, Rosa H. M. Song, Dong Berger, theodore W. City Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China Univ So Calif Dept Biomed Engn Los Angeles CA 90007 USA

ISBN: (纸本)9780769543017

We present a parallelized and pipelined architecture for a generalized Laguerre-Volterra MIMO system to identify the time-varying neural dynamics underlying spike activities. the proposed architecture consists of a first stage containing a vector convolution and MAC (Multiply and Accumulation) component;a second stage containing a pre-threshold potential updating unit with an error approximation function component;and a third stage consisting of a gradient calculation unit. A flexible and efficient architecture that can accommodate different design speed requirements are generated. Simulation results are rigorously analyzed. A hardware IP library for versatile models and applications is proposed. the design runs on a Xilinx Virtex-6 FPGA and the processing core produces data samples at a maximum clock rate of 357MHz, which is 4.37 x 10(5) times faster than the corresponding software model running on an AMD Pheono 9750 Quad Core Processor. It occupies 216,766 LUTs, maximum 12 block-RAMs, and 2016 DSP-blocks.

关键词： AMD Pheono 9750 Quad Core Processor Arrays Biological system modeling Computational modeling FPGA architecture Field programmable gate arrays Hardware MIMO systems Software Xilinx Virtex-6 FPGA biology computing error approximation function component field programmable gate arrays generalized Laguerre-Volterra MIMO model gradient calculation unit multiply and accumulation component neural nets neural population spiking activities parallel architectures parallelized architecture pipeline processing pipelined architecture time-varying neural dynamics vector convolution

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Synthesis of Platform architectures from OpenCL Programs

Synthesis of Platform Architectures from OpenCL Programs

引用

annual IEEE symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Muhsen Owaida Nikolaos Bellas Konstantis Daloukas Christos D. Antonopoulos Department of Computer and Communication Engineering University of Thessally Volos Greece

the problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this paper, we use OpenCL, an industry supported standard for writing programs that execute on multicore platforms and accelerators such as GPUs. Our architectural synthesis tool, SOpenCL (Silicon-OpenCL), adapts OpenCL into a novel hardware design flow which efficiently maps coarse and fine-grained parallelism of an application onto an FPGA reconfigurable fabric. SOpenCL is based on a source-to-source code transformation step that coarsens the OpenCL fine-grained parallelism into a series of nested loops, and on a template-based hardware generation back-end that configures the accelerator based on the functionality and the application performance and area requirements. Our experimentation with a variety of OpenCL and C kernel benchmarks reveals that area, throughput and frequency optimized hardware implementations are attainable using SOpenCL.

关键词： Hardware Kernel Synchronization Parallel processing Instruction sets Field programmable gate arrays Pixel

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Effects of Building Blocks on the Performance of Super-Scalar architectures

Effects of Building Blocks on the Performance of Super-Scala...

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annual International symposium on Computer Architecture, ISCA

作者： E.S.T. Fernandes F.M.B. Barbosa COPPE Sistemas and Instituto de Matemdtica Universidade Federal do Rio de Janeiro Rio de Janeiro Brazil

the inherent low level parallelism of Super-Scalar architectures plays an important role in the processing power provided by these machines: independent functional units promote opportunities for executing several machine operations simultaneously. From the view- point of the hardware designer it is very important to assess the influence of each functional unit, and the way they communicate, on the overall performance of the machine. Particularly, it is highly desirable to determine an upper bound in the number of additional functional units, which give significant performance improvement ratios. this work describes experiments that have been carried out to assess the effect of alternative instruction issue mechanisms, multiple functional units, instruction queues, common data bus and other hardware solutions on the performance of Super-Scalar machines. the assessment was obtained by interpreting non optimized object code of an actual processor on some basic machine models. the pa- per outlines the main aspects of the research, and shows that speed-up ratios of up to 3.35 times were observed during the interpretation of benchmark programs.

关键词： Hardware Computer architecture VLIW Permission Parallel processing Upper bound Distributed computing Machinery Parallel machines Process design

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GPU-Based architectures and their Benefit for Accurate and Efficient Wireless Network Simulations

GPU-Based Architectures and Their Benefit for Accurate and E...

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International symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)

作者： Philipp Andelfinger Jens Mittag Hannes Hartenstein Steinbuch Centre of Computing Karlsruhe Institute of Technology Germany Institute of Telematics Karlsruhe Institute of Technology Germany

In recent years, a trend towards the usage of physical layer models with increased accuracy can be observed within the wireless network community. this trend has several reasons. the consideration of signals - instead of packets - as the smallest unit of a wireless network simulation enables the ability to reflect complex radio propagation characteristics properly, and to study novel PHY/MAC/NET cross-layer optimizations that were not directly possible before, e.g. cognitive radio networks and interference cancellation. Yet, there is a price to pay for the increase of accuracy, namely a significant decrease of runtime performance due to computationally expensive signal processing. In this paper we study whether this price can be reduced - or even eliminated - if GPU-based signal processing is employed. In particular, we present and discuss four different architectures that can be used to exploit GPU-based signal processing in discrete event-based simulations. Our evaluation shows that the runtime costs can not be cut down completely, but significant speedups can be expected compared to a non GPU-based solution.

关键词： Graphics processing unit Computational modeling Signal processing Wireless networks Signal processing algorithms Computer architecture Runtime

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