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检索条件"任意字段=19th IASTED International Conference on Parallel and Distributed Computing and Systems"

共 564 条记录，以下是251-260 订阅

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Automatic Data Partitioning Applied to Multigrid PDE Solvers

Automatic Data Partitioning Applied to Multigrid PDE Solvers

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19th international Euromicro conference on parallel, distributed and Network-Based Processing (PDP)

作者： Fresno, Javier Gonzalez-Escribano, Arturo Llanos, Diego R. Univ Valladolid Dept Informat Valladolid Spain

ISBN: (纸本)9780769543284

this paper studies the impact of using automatic data-layout techniques on the process of coding the well-known multigrid MG NAS parallel benchmark. We describe the sequential problem in detail, and discuss the parallel version and its optimizations. then, we implement the parallel algorithm using Hitmap, a highly-efficient modular library for hierarchical tiling and mapping of arrays. We describe how to use the library plug-in system to add a new data-layout module that encapsulates a generalization of the data-alignment policy of the MG benchmark. the module system applies this policy to automatically adapt the data distribution and communication code to any grain level. the impact of using these techniques is qualitatively and quantitatively described in terms of development effort and performance. Our results show that it is possible to introduce flexible automatic data-layout techniques in current parallel compiler technology, without sacrificing performance.

关键词： Automatic data partition distributed systems layouts layouts distributed systems AUTOMATIC data distribution MODULE systems Data partitioning Magnesium MOTOR GENERATOR parallel algorithms Solvers MAPPING(MAthEMATICAL) Policies communications coding

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An analytical approach to the design of parallel block cipher encryption/decryption : A CPU/GPU case study

An analytical approach to the design of parallel block ciphe...

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19th international Euromicro conference on parallel, distributed and Network-Based Processing (PDP)

作者： Barlas, Gerassimos Hassan, Ahmed Al Jundi, Yasser Amer Univ Sharjah Dept Comp Sci & Engn Sharjah U Arab Emirates

ISBN: (纸本)9780769543284

GPUs are at the fore-front of a radical transformation that is taking place in software design. the ability to process multiple data streams simultaneously is delivering substantial benefits to a large collection of domains. Depending on the application, these benefits can be expanded by utilizing the not-insignificant power of traditional CPUs. Multi-core CPUs with a hierarchy of large and fast caches, can provide significant performance especially if data transfers dominate execution time, or branching does not allow for the uninterrupted execution on all GPU cores. In this paper we present an analytical framework that can be used to optimally consolidate CPU and GPU resources for the encryption/decryption of block ciphers such as AES. A rigorous set of experiments concludes the paper, show-casing the benefits and overall characteristics of the proposed framework. Our tests also bring to the surface important aspects of GPU operation that have to be taken into consideration upon the design of any successful scheduling scheme involving GPUs as a system component.

关键词： GPGPU block cipher AES divisible load theory heterogeneous computing

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A free openmp compiler and run-time library infrastructure for research on shared memory parallel computing

A free openmp compiler and run-time library infrastructure f...

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Proceedings of the 16th iasted international conference on parallel and distributed computing and systems

作者： Karlsson, Sven Brorsson, Mats Department of Microelectronics KTH Royal Institute of Technology Sweden

OpenMP is an informal industry standard for programming parallel computers with a shared memory and has during the last few years achieved considerable acceptance in both the academic world and the industry. OpenMP is a thread-level fork-join programming model and relies on a set of compiler directives. An OpenMP aware compiler uses these directives to generate a multi-threaded application. In practice, an OpenMP run-time library is also needed as OpenMP specifies a set of run-time library calls. In this paper we report on a free OpenMP compiler and run-time library infrastructure. We present an OpenMP compiler for C called OdinMP and briefly discuss the run-time library that the compiler targets. the source code to both the compiler and the run-time libraries are available and can be freely used for OpenMP research. the compilation system is evaluated using the EPCC micro-benchmark suite for OpenMP and a set of applications from the SPLASH-2 benchmarks suite ported to OpenMP. Comparisons are made to OpenMP aware compiler systems from SGI and Intel. the performance of code generated with the presented compilation system is shown to be very close to or exceeding that of commercial compilers for a wide range of benchmark applications.

关键词： parallel processing systems

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Analysis of parallel Binary Merge Sort in a Grid Environment 20

Analysis of Parallel Binary Merge Sort in a Grid Environment

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20th international conference on parallel and distributed computing systems, PDCS 2007

作者： Mach, Werner Schikuta, Erich University of Vienna Department of Knowledge and Business Engineering Rathausstraße 19/9 ViennaA-1010 Austria

ISBN: (纸本)9781604233926

this paper presents an analysis of the parallel binary merge sort algorithm and a comparison of its behavior in a generalized multiprocessor framework and a simplified Grid Environment. Based on the well known method of Bitton et al. (see [1]) we develop a concise but comprehensive analytical model. © 20th international conference on parallel and distributed computing systems, PDCS 2007. All rights reserved.

关键词： algorithm analysis grid infrastructure parallel sorting workflow orchestration

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Resource-Centered distributed Processing of Large Histopathology Images 19

Resource-Centered Distributed Processing of Large Histopatho...

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19th IEEE international conference on Computational Science and Engineering, 14th IEEE international conference on Embedded and Ubiquitous computing and 15th international Symposium on distributed computing and Applications to Business, Engineering and Science, CSE-EUC-DCABES 2016

作者： Salas, Daniel Gustedt, Jens Racoceanu, Daniel Perseil, Isabelle Inserm CISI Paris France INRIA Nancy - Grand Est France ICube - CNRS Université de Strasbourg France Université Pierre et Marie Curie Paris France

ISBN: (纸本)9781509035939

Automatic cell nuclei detection is a real challenge in medical imagery. the Marked Point Process (MPP) is one of the most promising scalable and paralellizable method. To handle large histopathology images, the algorithm has to be distributed. A new parallelization paradigm called Ordered Read-Write Locks (ORWL) is presented as a possible solution for solving some of the unwanted side effects of the distribution, namely an imprecision of the results on the internal boundaries of partitioned images. this solution extends a parallel version of MPP that has reached good speedups on GPU cards, but was not scaling to complete images as they appear in practical data. © 2016 IEEE.

关键词： Graphics processing units Convergence distributed computing Breast cancer System recovery conferences

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SMG: Shared memory for grids

SMG: Shared memory for grids

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Proceedings of the 16th iasted international conference on parallel and distributed computing and systems

作者： Ryan, John P. Coghlan, Brian A. Computer Architecture Group Dept. of Computer Science Trinity College Dublin Dublin 2 Ireland

this paper discusses some of the salient issues involved in implementing the illusion of a shared-memory programming model across a group of distributed memory processors from a cluster through to an entire Grid. this illusion can be provided by a distributed shared memory (DSM) runtime system. Mechanisms that have the potential to increase the performance by minimizing high-latency intra site messages & data transfers are highlighted. Relaxed consistency models are investigated, as well as the use of a grid information system to ascertain topology information. the latter allows for hierarchy-aware management of shared data and synchronization variables. the process of incremental hybridization is also explored, where more efficient message-passing mechanisms can incrementally replace DSM actions when circumstances dictate that performance improvements can be obtained. In this paper we describe the overall design/architecture of a prototype system, SMG, which integrates DSM and message passing paradigms and may be the target of an OpenMP compiler. Our initial findings based on some trivial examples indicate some of the potential benefits that can be obtained for grid Applications.

关键词： distributed computer systems

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Two parallel Implementations of Ehrlich-Aberth Algorithm for Root-Finding of Polynomials on Multiple GPUs with OpenMP and MPI 19

Two Parallel Implementations of Ehrlich-Aberth Algorithm for...

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作者： Ghidouche, Kahina Sider, Abderrahmane Khodja, Lilia Ziane Couturier, Raphaël Laboratoire LIMED Faculté des Sciences Exactes Université de Bejaia 06000 Algeria University Bourgogne Franche-Comte France

ISBN: (纸本)9781509035939

Finding the roots of polynomials is a very important part of solving real-life problems but the higher the degree of the polynomials is, the less easy it becomes. In this paper, we present two different parallel algorithms of the Ehrlich-Aberth method to find roots of sparse and fully defined polynomials of high degrees. Both algorithms are based on CUDA technology to be implemented on multi-GPU computing platforms but each use different parallel paradigms: OpenMP or MPI. the experiments show a quasi-linear speedup by using up-to 4 GPU devices compared to 1 GPU to find the roots of polynomials of degree up-to 1.4 million. Moreover, other experiments show it is possible to find the roots of polynomials of degree up-to 5 million. © 2016 IEEE.

关键词： Graphics processing unit

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A fault-tolerant ring-based algorithm for achieving mutual exclusion in distributed systems

A fault-tolerant ring-based algorithm for achieving mutual e...

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Proceedings of the 16th iasted international conference on parallel and distributed computing and systems

作者： Masum, Salahuddin Mohammad Al-Mamun, Mohammad Abdullah Islam, Khandoker Tarik-Ul Mostafa, Syed Md. Sazzad Akbar, Mohammad Mostofa Fac. of Sci. and Info. Technology Daffodil International University Dhaka 1207 Bangladesh Dept. of Comp. Sci. and Engineering IBAIS University Dhaka 1209 Bangladesh Department of Computer Science Amer. Intl. University - Bangladesh Dhaka 1213 Bangladesh Department of CSE Bangladesh Univ. Eng. and Technol. Dhaka 1000 Bangladesh

systems involving multiple processes are often most easily programmed using critical regions. Mutual exclusion is the dilemma of assurance that certain portions of program code are executed within the critical regions, where no two programs are permitted to be in critical regions at the same time. So, arranging mutual exclusion plays a significant role in the domain of both centralized and distributed systems. Unfortunately, all the three basic approaches - centralized, distributed and token ring proposed for achieving mutual exclusion in distributed systems are said to be good for distributed systems in some abstract way only. In this paper, we have presented a ring-based algorithm for arranging mutual exclusion in distributed systems. We have compared the conventional algorithms with the algorithm presented in this paper and shown that our algorithm is more fault-tolerant than all the traditional algorithms and requires less number of message-passing with reduced amount of load on coordinator.

关键词： Fault tolerant computer systems

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Issues and Challenges in Development of Massively-parallel Heterogeneous MPSoCs Based on Adaptable ASIPs

Issues and Challenges in Development of Massively-Parallel H...

引用

19th international Euromicro conference on parallel, distributed and Network-Based Processing (PDP)

作者： Jozwiak, Lech Lindwer, Menno Eindhoven Univ Technol Eindhoven Netherlands Silicon Hive BV Eindhoven Netherlands

ISBN: (纸本)9780769543284

the recent spectacular progress in modern nanoelectronic technology enabled implementation of very complex multiprocessor systems on single chips (MPSoCs) and created a big stimulus towards development of MPSoCs for embedded applications. the increasingly complex MPSoCs are required to perform real-time computations to extremely tight schedules and to satisfy high demands regarding adaptability, as well as energy, area and cost efficiency. this results in serious design and development challenges. the opportunities created can effectively be exploited only through use of more adequate system architectures and more integrated system IP modules, supported by new effective design methods and electronic design automation tools. this paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable application-specific instruction-set processors (ASIPs). It is related to a European project ASAM being currently executed in the framework of the ARTEMIS program. It presents the results of our analysis of the main problems that have to be solved and challenges to be faced in design of such heterogeneous customizable MPSoCs for modern demanding applications.

关键词： embedded systems heterogeneous multi-processor system-on-chip (MPSoC) customizable ASIPs architecture synthesis MPSoC and ASIP design automation

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Reconfigurable parallel prefix computation on FPGAs

Reconfigurable parallel prefix computation on FPGAs

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Proceedings of the 16th iasted international conference on parallel and distributed computing and systems

作者： Park, Jin H. Or, Mei S. Department of Computer Science State Univ. of New York at New Paltz New Paltz NY 12561-2440 United States

this paper presents a design of a reconfigurable parallel prefix computation hardware on FPGAs. the design is based on a pipelined dataflow algorithm, and control logics are added to reconfigure the system for the arbitrary parallelism degree. the design receives multiple input streams of elements in parallel, and produces output streams in parallel. the design has the great advantage of controlling the degree of parallelism explicitly at run time. Time complexity of the design is O(d + (N-d) / d), where d and N are parallelism degree and stream size, respectively. When the stream size is very big, the initial trigger time d in the time complexity can be ignored and we get O(N/d). Unlike the software parallel prefix algorithms, the design works for both known and unknown sized data. the design is implemented and tested for target devices Xilinx Spartan2S XC2S300EFT256-6Q and XC2S600EFG676-6.

关键词： Field programmable gate arrays

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