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On Designing Multicore-Aware Simulators for Biological systems

On Designing Multicore-Aware Simulators for Biological Syste...

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Euromicro conference on parallel, distributed and Network-Based Processing

作者： Marco Aldinucci Mario Coppo Ferruccio Damiani Maurizio Drocco Massimo Torquati Angelo Troina Computer Science Department University of Torino Italy Computer Science Department University of Pisa Italy

the stochastic simulation of biological systems is an increasingly popular technique in bioinformatics. It often is an enlightening technique, which may however result in being computational expensive. We discuss the main opportunities to speed it up on multi-core platforms, which pose new challenges for parallelisation techniques. these opportunities are developed in two general families of solutions involving both the single simulation and a bulk of independent simulations (either replicas of derived from parameter sweep). Proposed solutions are tested on the parallelisation of the CWC simulator (Calculus of Wrapped Compartments) that is carried out according to proposed solutions by way of the Fast Flow programming framework making possible fast development and efficient execution on multi-cores.

关键词： Computational modeling parallel processing Biological system modeling Stochastic processes parallel programming Data models

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Performance Prediction of distributed Applications Using Block Benchmarking Methods

Performance Prediction of Distributed Applications Using Blo...

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Euromicro conference on parallel, distributed and Network-Based Processing

作者： Bogdan Florin Cornea Julien Bourgeois LIFC University of Franche-Comté Montbeliard France

An ongoing work is presented for accurately predicting the performance of distributed applications in heterogeneous systems. We are developing dPerf, a tool built using the Rose framework for performing static analysis and an automatic instrumentation on the input source code of programs written in C, C++ or Fortran. the accuracy in predicting program computation time resides in using hardware counters, as well as in applying two block benchmarking techniques that we propose in this paper. the current work makes use of a network simulator in order to calculate the communication time used in our approach. Afterwards, the computation and communication times are being summed up obtaining an estimation of the distributed application execution time. the approach is proven experimentally using NAS Integer Sort benchmark, the communications being simulated with SimGrid.

关键词： Benchmark testing Instruments Radiation detectors Computational modeling Program processors Hardware Analytical models

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Rule-Based Mapping of Virtual Machines in Clouds

Rule-Based Mapping of Virtual Machines in Clouds

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Euromicro conference on parallel, distributed and Network-Based Processing

作者： Christoph Kleineweber Axel Keller Oliver Niehorster Andre Brinkmann Paderborn Center of Parallel Computing Universität Paderborn Germany

Infrastructure as a Service providers use virtualization to abstract their hardware and to create a dynamic data center. Virtualization enables the consolidation of virtual machines as well as the migration of them to other hosts during runtime. Each provider has its own strategy to efficiently operate a data center. We present a rule based mapping algorithm for VMs, which is able to automatically adapt the mapping between VMs and physical hosts. It offers an interface where policies can be defined and combined in a generic way. the algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. the evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the parallel Workload Archive. the results show that our algorithm performs well in dynamic data centers environments.

关键词： Measurement Sensors Energy consumption Virtual machining Power demand Monitoring Runtime

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Operating systems and Virtualization Frameworks: From Local to distributed Similarities

Operating Systems and Virtualization Frameworks: From Local ...

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Euromicro conference on parallel, distributed and Network-Based Processing

作者： Flavien Quesnel Adrien Lebre ASCOLA Research Team INRIA LINA Ecole des Mines de Nantes Nantes France

Virtualization technologies radically changed the way in which distributed architectures are exploited. With the contribution of VM capabilities and with the emergence of IaaS platforms, more and more frameworks tend to manage VMs across distributed architectures like operating systems handle processes on a single node. Taking into account that most of these frameworks follow a centralized model -- where roughly one node is in charge of the management of VMs -- and considering the growing size of infrastructures in terms of nodes and VMs, new proposals relying on more autonomic and decentralized approaches should be submitted. Designing and implementing such models is a tedious and complex task. However, as well as research studies on OSes and hyper visors are complementary at the node level, we advocate that virtualization frameworks can benefit from lessons learnt from distributed operating system proposals. In this article, we motivate such a position by analyzing similarities between OSes and virtualization frameworks. More precisely, we focus on the management of processes and VMs, first at the node level and then on a cluster scale. From our point of view, such investigations can guide the community to design and implement new proposals in a more autonomic and distributed way.

关键词： Virtual machine monitors Virtual machining Memory management Operating systems Linux Runtime Dynamic scheduling

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A Javaspace-Based Framework for Efficient Fault-Tolerant Master-Worker distributed Applications

A Javaspace-Based Framework for Efficient Fault-Tolerant Mas...

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Euromicro conference on parallel, distributed and Network-Based Processing

作者： Virginie Galtier Constantinos Makassikis Stephane Vialle UMI-2958 SUPELEC France

We propose a framework built around a Java Space to ease the development of bag-of-tasks applications. the framework may optionally and automatically tolerate transient crash failures occurring on any of the distributed elements. It relies on check pointing and underlying middleware mechanisms to do so. To further improve check pointing efficiency, both in size and frequency, the programmer can introduce intermediate user-defined checkpoint data and code within the task processing program. the framework used without fault tolerance accelerates application development, does not introduce runtime overhead and yields to expected speedup. When enabling fault tolerance, our framework allows, despite failures, correct completion of applications with limited runtime and data storage overheads. Experiments run with up to 128 workers study the impact of some user-related and implementation-related on overall performance, and reveal good performances for classical Java Space-based master-worker application profiles.

关键词： Runtime Fault tolerance Fault tolerant systems Checkpointing Java Transient analysis Middleware

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High Performance Matrix Inversion on a Multi-core Platform with Several GPUs

High Performance Matrix Inversion on a Multi-core Platform w...

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Euromicro conference on parallel, distributed and Network-Based Processing

作者： Pablo Ezzatti Enrique S. Quintana-Ortí Alfredo Remon Centro de Cálculo Universidad de la República Montevideo Uruguay Uruguay Depto. de Ingeniería y Universidad Jaume I Castellón Spain

Inversion of large-scale matrices appears in a few scientific applications like model reduction or optimal control. Matrix inversion requires an important computational effort and, therefore, the application of high performance computing techniques and architectures for matrices with dimension in the order of thousands. Following the recent uprise of graphics processors (GPUs), we present and evaluate high performance codes for matrix inversion, based on Gauss-Jordan elimination with partial pivoting, which off-load the main computational kernels to one or more GPUs while performing fine-grain operations on the general-purpose processor. the target architecture consists of a multi-core processor connected to several GPUs. parallelism is extracted from parallel implementations of BLAS and from the concurrent execution of operations in the available computational units. Numerical experiments on a system with two Intel QuadCore processors and four NVIDIA cl060 GPUs illustrate the efficiency and the scalability of the different implementations, which deliver over 1.2 x 10 12 floating point operations per second.

关键词： Graphics processing unit Multicore processing Partitioning algorithms parallel processing Electronic mail

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Issues and Challenges in Development of Massively-parallel Heterogeneous MPSoCs Based on Adaptable ASIPs

Issues and Challenges in Development of Massively-Parallel H...

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Euromicro conference on parallel, distributed and Network-Based Processing

作者： Lech Jóźwiak Menno Lindwer Eindhoven University of Technology Eindhoven The Netherlands Silicon Hive B.V. Eindhoven The Netherlands

the recent spectacular progress in modern Nan electronic technology enabled implementation of very complex multiprocessor systems on single chips (MPSoCs) and created a big stimulus towards development of MPSoCs for embedded applications. the increasingly complex MPSoCs are required to perform real-time computations to extremely tight schedules and to satisfy high demands regarding adaptability, as well as energy, area and cost efficiency. this results in serious design and development challenges. the opportunities created can effectively be exploited only through use of more adequate system architectures and more integrated system IP modules, supported by new effective design methods and electronic design automation tools. this paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable application-specific instruction-set processors (ASIPs). It is related to a European project ASAM being currently executed in the framework of the ARTEMIS program. It presents the results of our analysis of the main problems that have to be solved and challenges to be faced in design of such heterogeneous customizable MPSoCs for modern demanding applications.

关键词： Computer architecture Hardware Program processors Embedded systems Registers Algorithm design and analysis

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In Situ Power Analysis of General Purpose Graphical Processing Units

In Situ Power Analysis of General Purpose Graphical Processi...

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Euromicro conference on parallel, distributed and Network-Based Processing

作者： M.Z. Shaikh M. Gregoire W. Li M. Wroblewski S. Simon Institute of Parallel and Distributed Systems University of Stuttgart Stuttgart Germany

In this paper, an in situ power analysis profiling over time for general purpose graphics processing units (GPGPU) is presented. Based on this method the power consumption of different modes of operations like data transfer between GPU and host CPU, basic single precision floating point arithmetic operations (addition, subtraction, multiplication) on the multiprocessor units and instructions for shared and global memory access can be measured. there is a factor of 2 difference in power dissipation between various instructions and mode of operations of the GPGPUs. these measurements provide data for an instruction based power estimation of GPU software. It turns out that the power profile over time also gives a good understanding on which section of the program is executed at a certain point in time. the experimental results have been derived from two GPU architectures, namely the GT200 and the GF100 architecture.

关键词： Graphics processing unit Power dissipation Computer architecture Finite difference methods Time domain analysis Kernel Power measurement

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Load Balancing for Data-parallel Applications on Network-on-Chip Enabled Multi-processor Platform

Load Balancing for Data-Parallel Applications on Network-on-...

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Euromicro conference on parallel, distributed and Network-Based Processing

作者： Jungsook Yang Chuny Chun Nader Bagherzadeh Seung Eun Lee Electrical Engineering and Computer Science University of California Irvine Irvine CA USA Electronic and Information Engineering Seoul National University of Technology South Korea

As the computation cost increases to meet the design requirements for computation-intensive applications on today's systems, the pressure to develop high performance parallel processors on a chip will increase. Network-on-Chip (NoC) techniques that interconnect multiple processing elements with routers are the solution for reducing computation time and power consumption by parallel processing on a chip. the shared communication platform is also essential to meet the scalability and complexity challenges for System-on-Chip (SoC). However not many parallel applications have been studied for such an architecture and workload characterizations have not been researched to benefit the architecture design optimization. In this paper, we study multiple data-parallel applications on a multicore NoC architecture with distributed memory space. We introduce an efficient runtime workload distribution algorithm that balances workloads of parallel processors and apply for selected embedded applications. Using our cycle accurate multicore simulator, we simulated our NoC-enabled multicore architecture model and executed data-parallel applications on various number of processing elements using the proposed runtime load balancing algorithm and analyzed performance and communication overheads.

关键词： Program processors Nickel Multicore processing System-on-a-chip Network interfaces parallel processing

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Dynamic I/O Reconfiguration for a NFS-Based parallel File System

Dynamic I/O Reconfiguration for a NFS-Based Parallel File Sy...

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Euromicro conference on parallel, distributed and Network-Based Processing

作者： Rodrigo Kassick Francieli Zanon Boito Philippe O.A. Navaux Instituto de Informática Universidade Federal do Rio Grande do Sul Brazil

the large gap between the speed in which data can be processed and the performance of I/O devices makes the shared storage infrastructure of a cluster a great bottle-neck. parallel File systems try to smooth such difference by distributing data onto several servers, increasing the system's available bandwidth. However, most implementations use a fixed number of I/O servers, defined during the initialization of the system, and can not add new resources without a complete redistribution of the existing data. With the execution of different applications at the same time, the concurrent access to these resources can aggravate the existing bottleneck, making very hard to define an initial number of servers that satisfies the performance requirements of different applications. this paper presents a reconfiguration mechanism for the dNFSp file system that uses on-line monitoring of application's I/O behavior to detect performance contention and dedicate more I/O resources to applications with higher demands. these extra resources are taken from the available nodes of the cluster, using their I/O devices as a temporary storage. We show that this strategy is capable of increasing the I/O performance in up to 200% for access patterns with short I/O phases and 47% for longer I/O phases.

关键词： Servers Bandwidth Performance evaluation File systems Computer architecture Monitoring Benchmark testing

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