Most existing approaches to targeting high-level software to FPGAs are based on extensions to C and do not map easily to the features and characteristics of modern FPGAs. these include massive parallelism and a variet...
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ISBN:
(纸本)9781424438914
Most existing approaches to targeting high-level software to FPGAs are based on extensions to C and do not map easily to the features and characteristics of modern FPGAs. these include massive parallelism and a variety of complex IP-blocks (eg. RAMs, DSPs). In this paper we discuss a hardware implementation of SR, a software language with first class concurrency and high-level IPC. We show that the language model can be implemented efficiently on an FPGA, and that it provides a natural means to encapsulate FPGA resources. We compare against a commercial C-based synthesis tool and achieve similar resource usage using a more expressive language.
One recent development in logicprogramming has been the application of abstract interpretation to verify the partial correctness of a logic program with respect to a given set of assertions. One approach to verificat...
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ISBN:
(纸本)3540206426
One recent development in logicprogramming has been the application of abstract interpretation to verify the partial correctness of a logic program with respect to a given set of assertions. One approach to verification is to apply forward analysis that starts with an initial goal and traces the execution in the direction of the control-flow to approximate the program state at each program point. this is often enough to verify that the assertions hold. the dual approach is to apply backward analysis to propagate properties of the allowable states against the control-flow to infer queries for which the program will not violate any assertion. this paper is a systematic comparison of these two approaches to verification. the paper reports some equivalence results that relate the relative power of various forward and backward analysis frameworks.
A same-syntax extension of RDF to first-order logic results in a collapse of the model theory due to logical paradoxes resulting from diagonalization. RDF is thus the wrong material for building the Semantic Web tower.
A same-syntax extension of RDF to first-order logic results in a collapse of the model theory due to logical paradoxes resulting from diagonalization. RDF is thus the wrong material for building the Semantic Web tower.
In this paper we sketch a vision of explainability of intelligent systems as a logic approach suitable to be injected into and exploited by the system actors once integrated with sub-symbolic techniques. In particular...
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ISBN:
(数字)9783030770914
ISBN:
(纸本)9783030770914;9783030770907
In this paper we sketch a vision of explainability of intelligent systems as a logic approach suitable to be injected into and exploited by the system actors once integrated with sub-symbolic techniques. In particular, we show how argumentation could be combined with different extensions of logicprogramming - namely, abduction, inductive logicprogramming, and probabilistic logicprogramming - to address the issues of explainable AI as well as some ethical concerns about AI.
this paper presents the method of FPGA-oriented synthesis of multiple-valued logical networks. Multiple-valued network consists of modules connected by multiple-valued signals. During synthesis each module is decompos...
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ISBN:
(纸本)9781509028160
this paper presents the method of FPGA-oriented synthesis of multiple-valued logical networks. Multiple-valued network consists of modules connected by multiple-valued signals. During synthesis each module is decomposed into smaller ones, that may be implemented using one logic cell. For this purpose the symbolic decomposition is applied. Since the decomposition of modules strongly depends on encoding of multivalued inputs and outputs, the result of synthesis depends on the order, in which the consecutive modules are implemented. In our approach we optimize this order using developmental genetic programming. Experimental results showed that our approach significantly reduces the cost of implementation.
this work presents a narrowing calculus for reachability problems in order-sorted conditional rewrite theories whose underlying equational logic is composed of some theories solvable via a satisfiability modulo theori...
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ISBN:
(纸本)9781450352918
this work presents a narrowing calculus for reachability problems in order-sorted conditional rewrite theories whose underlying equational logic is composed of some theories solvable via a satisfiability modulo theories (SMT) solver plus some combination of associativity, commutativity, and identity axioms for the non-SMT part of the equational logic;the conditions of the rules can be either rewrite conditions or quantifier-free SMT formulas. For any normalized answer of a reachability problem, this calculus computes this answer, or a more general one that can be instantiated to it.
We propose a parametric introduction of intensionally defined sets into any CLP(D) language. the result is a language CLP({D}), where constraints over sets of elements of D and over sets of sets of elements, and so on...
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ISBN:
(纸本)3540206426
We propose a parametric introduction of intensionally defined sets into any CLP(D) language. the result is a language CLP({D}), where constraints over sets of elements of D and over sets of sets of elements, and so on, can be expressed. the semantics of CLP({D}) is based on the semantics of logic programs with aggregates and the semantics of CLP over sets. We investigate the problem of constraint resolution in CLP({D}) and propose algorithms for constraints simplification.
We present new procedures for identifying redundant stuck-at faults including multiple line stuck-at faults on the branches of fan-out stems. the methods proposed include new procedures to identify stuck-at faults tha...
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ISBN:
(纸本)0769525024
We present new procedures for identifying redundant stuck-at faults including multiple line stuck-at faults on the branches of fan-out stems. the methods proposed include new procedures to identify stuck-at faults that are simultaneously redundant thus allowing simultaneous removal of logic associated with several redundant faults. Experimental results on benchmark as well as industrial circuits are also presented to demonstrate the effectiveness of the proposed methods.
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