the proceedings contain 36 papers. the topics discussed include: robust low power embedded SRAM design: from system to memory cell;variability in advanced nanometer technologies: challenges and solutions;subthreshold ...
ISBN:
(纸本)3642118011
the proceedings contain 36 papers. the topics discussed include: robust low power embedded SRAM design: from system to memory cell;variability in advanced nanometer technologies: challenges and solutions;subthreshold circuit design for ultra-low-power applications;SystemC AMS extensions: new language - new methods - new applications;process variation aware performance analysis of asynchronous circuits considering spatial correlation;interpreting SSTA results with correlation;residue arithmetic for variation-tolerant design of multiply-add units;exponent Monte Carlo for quick statistical circuit simulation;clock repeater characterization for jitter-aware clock tree synthesis;a hardware implementation of the user-centric display energy management;on-chip thermal modeling based on spice simulation;switching noise optimization in the wake-up phase of leakage-aware power gating structures;and data-driven clock gating for digital filters.
the proceedings contain 45 papers. the topics discussed include: subthreshold FIR filter architecture for ultra low pow applications;improving the power-delay performance in subthreshold source-coupled logic circuits;...
the proceedings contain 45 papers. the topics discussed include: subthreshold FIR filter architecture for ultra low pow applications;improving the power-delay performance in subthreshold source-coupled logic circuits;design and evaluation of mixed 3T-4T FinFET stacks for leakage reduction;temporal discharge current driven clustering for improved leakage power reduction in row-based power-gating;Intelligate: scalable dynamic invariant learning for power reduction;analysis of effects of input arrival time variations on on-chip bus power consumption;untraditional approach to computer energy reduction;poweroptimization of parallel multipliers in systems with variable word-length;a study on CMOS time uncertainty with technology scaling;a comparison between two logic synthesis forms from digital switching noise viewpoint;and ultra low voltage high speed differential CMOS inverter.
this book constitutes the thoroughly refereed post-conference proceedings of 19th international workshop on power and timing modeling, optimization and simulation, patmos 2009, featuring Integrated Circuit and System ...
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ISBN:
(数字)9783642118029
ISBN:
(纸本)9783642118012
this book constitutes the thoroughly refereed post-conference proceedings of 19th international workshop on power and timing modeling, optimization and simulation, patmos 2009, featuring Integrated Circuit and System Design, held in Delft, the Netherlands during September 9-11, 2009. the 26 revised full papers and 10 revised poster papers presented were carefully reviewed and selected from numerous submissions. the papers are organized in topical sections on variability & statistical timing, circuit level techniques, power management, low power circuits & technology, system level techniques, power & timingoptimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies.
Parallel multipliers can be optimized using the intrinsic arithmetic equivalencies in their reduction-tree. In this paper, we propose a method to reduce the dynamic power consumption in parallel multipliers, operating...
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ISBN:
(纸本)9783540959472
Parallel multipliers can be optimized using the intrinsic arithmetic equivalencies in their reduction-tree. In this paper, we propose a method to reduce the dynamic power consumption in parallel multipliers, operating within systems with effective word-length variation. Word-length variation induces a certain pattern of spatiotemporal correlations. the proposed method is capable to take such correlations into account resulting better solutions. the experimental results show about 16-21% reduction in the average number of transitions compared to random parallel multipliers.
powermodeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates: the power dissipated by input transitions that do not produce output switching. I...
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ISBN:
(纸本)9783540959472
powermodeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates: the power dissipated by input transitions that do not produce output switching. In this work, we present an experimental set-up that shows that this power component may contribute tip to 59% of the total power consumption of a gate in modern technologies. this fact makes very important to include it into any accurate power model.(1)
this paper investigates the performance of a novel set of Residue Number System (RNS) bases, emphasizing on the minimization of the power x delay product. the proposed bases introduce moduli of the form 3(n), to the u...
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ISBN:
(纸本)9783540959472
this paper investigates the performance of a novel set of Residue Number System (RNS) bases, emphasizing on the minimization of the power x delay product. the proposed bases introduce moduli of the form 3(n), to the usual choice of moduli of the form 2(n), 2(n) - 1, or 2(n) + 1. It is found that for particular dynamic ranges, the introduction of high-radix modulo-3(n) multipliers significantly improves the power x delay performance of residue multiplication, in comparison to conventional two's-complement implementations as well as to RNS architectures using bases composed of radix-2 moduli. Experimental results demonstrate reduction of the power x delay product by almost a factor of two, for some cases.
Virtual channels are a common alternative for providing quality-of-service to Networks-on-Chip. A drawback of the approach is the increased power consumption because of the suppression of correlation between consecuti...
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ISBN:
(纸本)9783540959472
Virtual channels are a common alternative for providing quality-of-service to Networks-on-Chip. A drawback of the approach is the increased power consumption because of the suppression of correlation between consecutive flits. this work proposes an architecture based on low-power coding to overcome the aforementioned problem. the technique requires a minimum overhead, while obtaining a significant power reduction (45% in the average case). Exhaustive experimental simulations are provided to demonstrate the advantages of the proposed architecture.
In this work we introduce an enhanced methodology to detect dynamic invariants from a power-benchmark simulation trace database. the method is scalable for the application of clock-gating extraction on industrial desi...
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ISBN:
(纸本)9783540959472
In this work we introduce an enhanced methodology to detect dynamic invariants from a power-benchmark simulation trace database. the method is scalable for the application of clock-gating extraction on industrial designs. Our approach focuses upon dynamic simulation data as the main source for detection of opportunities for power reduction. Experimental results demonstrate our ability to learn accurate clock-gating functions from simulation traces and achieve significant power reduction (in the range of 30%-70% of a clock net's power) on industrial micro-processor designs.
this paper proposes a new kind of side-channel attack where the correlation between processed data and total capacitance seen looking into the power supply pin of a cryptographic device is exploited. the attack is int...
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ISBN:
(纸本)9783540959472
this paper proposes a new kind of side-channel attack where the correlation between processed data and total capacitance seen looking into the power supply pin of a cryptographic device is exploited. the attack is introduced and advantages and drawbacks with respect to the well-known power analysis are discussed. the attack implementation and experimental results attacking a static CMOS implementation of a 8051 microprocessor core are provided and a comparison between the proposed technique and power analysis is carried out. the obtained results are promising and future activities are planned to assess the performance of this new side-channel analysis when attacking secure implementations.
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