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检索条件"任意字段=1st IEEE/ACM/IFIP International Conference on Hardward/Software Codesign and System Synthesis"

共 26 条记录，以下是1-10 订阅

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RTOS scheduling in transaction level models 03

RTOS scheduling in transaction level models

引用

1st ieee/acm/ifip international conference on hardward/software codesign and system synthesis

作者： Yu, HB Gerstlauer, A Gajski, D Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92697 USA

ISBN: (纸本)1581137427

Raising the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impact on system performance, it's much desired that the designer can select the right scheduling algorithm at high abstraction levels so as to save him from the error-prone and time consuming task of tuning code delays or task priority assignments at the final stage of system design. In this paper we tackle this problem by introducing a RTOS model and an approach to refine any unscheduled transaction level model (TLM) to a TLM with RTOS scheduling support. The refinement process provides a useful tool to the system designer to quickly evaluate different dynamic scheduling algorithms and make the optimal choice at the early stage of system design.

关键词： RTOS SpecC system design model

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Extending the systemC synthesis subset by object-oriented features

Extending the SystemC synthesis subset by object-oriented fe...

引用

1st ieee/acm/ifip international conference on hardward/software codesign and system synthesis

作者： Grimpe, E Oppenheimer, F OFFIS Res Inst D-26121 Oldenburg Germany

ISBN: (纸本)1581137427

In this article we present an approach to object-oriented hardware design and synthesis based on systemC. We will give an introduction to an extended systemC synthesis subset which we propose, and;in particular, its object-oriented features. We will also briefly outline our basic synthesis concepts for object-oriented hardware specifications. Finally we will present some examples for the application of the extended synthesis subset, which are directly processable by a first synthesis tool prototype which we have developed for this purpose.

关键词： systemC C/C plus plus based design hardware description language hardware synthesis system level design object-orientation high-level synthesis

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Hardware support for real-time operating systems

Hardware support for real-time operating systems

引用

1st ieee/acm/ifip international conference on hardward/software codesign and system synthesis

作者： Kohout, P Ganesh, B Jacob, B EVI Technol LLC Columbia MD 21046 USA

ISBN: (纸本)1581137427

The growing complexity of embedded applications and pressure on time-to-market has resulted in the increasing use of embedded real-time operating systems. Unfortunately, RTOSes can introduce a significant performance degradation. This paper presents the Real-Time Task Manager (RTM)-a processor extension that minimizes the performance drawbacks associated with RTOSes. The RTM accomplishes this by supporting, in hardware, a few of the common RTOS operations that are performance bottlenecks: task scheduling, time management, and event management. By exploiting the inherent parallelism of these operations, the RTM completes them in constant time, thereby significantly reducing RTOS overhead. It decreases both the processor time used by the RTOS and the maximum response time by an order of magnitude.

关键词： RTOS hardware software codesign

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A low-cost memory architecture with NAND XIP for mobile embedded systems

A low-cost memory architecture with NAND XIP for mobile embe...

引用

1st ieee/acm/ifip international conference on hardward/software codesign and system synthesis

作者： Park, C Seo, J Bae, S Kim, H Kim, S Kim, B Samsung Elect Co Ltd Software Ctr Seoul 135893 South Korea

ISBN: (纸本)1581137427

NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and high density. Even though NAND flash memory is gaining popularity as data storage, it can be also exploited as code memory for XIP (execute-in-place). In this paper, we present a new memory architecture which incorporates NAND flash memory into an existing memory hierarchy for code execution. The usefulness of the proposed approach is demonstrated with real embedded workloads on a real prototyping board.

关键词： memory architecture NAND XIP priority-based caching

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Deriving process networks from weakly dynamic applications in system-level design

Deriving process networks from weakly dynamic applications i...

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1st ieee/acm/ifip international conference on hardward/software codesign and system synthesis

作者： stefanov, T Deprettere, E Leiden Univ Leiden Inst Adv Comp Sci Leiden Embedded Res Ctr NL-2300 RA Leiden Netherlands

ISBN: (纸本)1581137427

We present an approach to the automatic derivation of executable Process Network specifications from Weakly Dynamic Applications. We introduce the notions of Dynamic Single Assignment Code, Approximated Dependence Graph, and Linearly Bounded Sets to model and capture weakly dynamic (data-dependent) behavior of applications at the task-level of abstraction. Process Networks are simple parallel processing models that match the emerging multi-processor architectures in the sense that the mapping of Process Network specifications of applications onto multi-processor architectures can be done in a systematic and transparent way.

关键词： system-level design heterogeneous embedded systems kahn process networks weakly dynamic applications

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Pareto-optimization-based run-time task scheduling for embedded systems 03

Pareto-optimization-based run-time task scheduling for embed...

引用

1st ieee/acm/ifip international conference on hardward/software codesign and system synthesis

作者： Yang, P Catthoor, F IMEC B-3001 Louvain Belgium

ISBN: (纸本)1581137427

Pareto-set-based optimization can be found in several different areas of embedded system design. One example is task scheduling, where different task mapping and ordering choices for a target platform will lead to different performance/cost tradeoffs. To explore this design space at run-time, a fast and effective heuristic is needed. We have modeled the problem as the well known Multiple Choice Knapsack Problem(MCKP) and have developed a fast greedy heuristic for the run-time task scheduling. To show the effectiveness of our algorithm, examples from randomly generated task graphs and realistic applications are studied. Compared to the optimal dynamic programming solver, the heuristic is more than ten times faster while the result is less than 5% away from the optimum. Moreover, due to its iterative feature, the algorithm is well suitable to be used as an on-line algorithm.

关键词： Pareto optimization scheduling embedded system lowpower

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A codesigned on-chip logic minimizer

A codesigned on-chip logic minimizer

引用

1st ieee/acm/ifip international conference on hardward/software codesign and system synthesis

作者： Lysecky, R Vahid, F Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)1581137427

Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic use in embedded systems, including network route table reduction, network access control list table reduction, and dynamic hardware/software partitioning. These now uses require logic minimization to run dynamically as part of an embedded system's active operation. Performing such dynamic logic minimization on-chip greatly reduces system complexity and security versus an approach that involves communication with a desktop logic minimizer. An on-chip minimizer must be exceptionally lean yet yield good enough results. Previous software-only on-chip minimizer results have been good, but we show that a codesigned minimizer can be much better, executing nearly 8 times faster and consuming nearly 60% less energy, while yielding identical results.

关键词： logic minimization dynamic optimization on-chip logic minimization on-chip synthesis system-on-a-chip embedded systems hardware/software codesign embedded CAD

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Security wrappers and power analysis for SoC technologies

Security wrappers and power analysis for SoC technologies

引用

1st ieee/acm/ifip international conference on hardward/software codesign and system synthesis

作者： Gebotys, CH Zhang, Y Univ Waterloo Dept Elect & Comp Engn Waterloo ON N2L 3G1 Canada

ISBN: (纸本)1581137427

Future wireless internet enabled devices will be increasingly powerful supporting many more applications including one of the most crucial, security. Although SoCs offer more resistance to bus probing attacks, power/EM attacks on cores and network snooping attacks by malicious code are relevant. This paper presents a methodology for security on NoC at both the network level (or transport layer) and at the core level (or application layer) is proposed. For the first time a low cost security wrapper design is presented, which prevents unencrypted keys from leaving the cores and NoC. This is crucial to prevent untrusted software on or off the NoC from gaining access to keys. At the core level (application layer) power analysis attacks are examined for the first time for parallel and adiabatic architectural cores. With the emergence of secure IP cores in the market, a security methodology for designing NoCs is crucial for supporting future wireless internet enabled devices.

关键词： design security performance VLIW adiabatic

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SEAS: A system for early analysis of SoCs

SEAS: A system for early analysis of SoCs

引用

1st ieee/acm/ifip international conference on hardward/software codesign and system synthesis

作者： Bergamaschi, RA Shin, YS Dhanwada, N Bhattacharya, S Dougherty, WE Nair, I Darringer, J Paliwal, S IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)1581137427

systems-on-chip (SoC) continue to be very complex to design and verify, despite extensive component reuse. Although reusable components are pre-designed and pre-verified, when they are assembled in an SoC there is no guarantee that the whole system will behave as expected from a performance, cost and integration point of view. In many cases this is because of faulty early design decisions regarding the architecture, core selection, floorplanning, etc. This paper presents a system for early analysis of SoCs which helps designers make early design decisions regarding performance, area, timing and power;and allows them to quickly evaluate cross-domain effects, such as the effect that an architectural decision may have on the performance and chip area.

关键词： design analysis design space exploration performance power floorplanning

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A low-cost and low-power multi-standard video encoder

A low-cost and low-power multi-standard video encoder

引用

1st ieee/acm/ifip international conference on hardward/software codesign and system synthesis

作者： Llopis, RP Sethuraman, R Pinto, CA Peters, H Maul, S Oosterhuis, M Philips Res Labs NL-5656 AA Eindhoven Netherlands

ISBN: (纸本)1581137427

Video encoders are an important IP block in mobile multimedia systems. In this paper, we describe a low-cost low-power multi-standard (MPEG4, JPEG, and H.263) video/image encoder. The low-cost and low-power aspects are achieved by the right choice of algorithms and architectures. In the algorithm front, an embedded compression technique for reducing the size of loop memory has enabled a single-chip low-cost realization of the encoder. In the architectural front, an efficient hardware-software partitioning has contributed to the design of a low-power encoder. Further, the hardware components that accelerate the kernels of encoding are implemented as application specific instruction-set processors (ASIPs) thereby providing flexibility to address multi-standard encoding. The power and area estimates for the encoder for QCIF@15fps in 0.18mum CMOS technology are 30mW and 20mm(2) respectively including the loop memory.

关键词： video encoder multi-standard low-power low-cost ASIPs hardware/software partitioning

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