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检索条件"任意字段=2003 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming"

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HPVM: Heterogeneous parallel Virtual Machine 18

HPVM: <i>Heterogeneous Parallel Virtual Machine</i>

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23rd acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Kotsifakou, Maria Srivastava, Prakalp Sinclair, Matthew D. Komuravelli, Rakesh Adve, Vikram Adve, Sarita Univ Illinois Dept Comp Sci Champaign IL 61820 USA Qualcomm Technol Inc San Diego CA USA

ISBN: (纸本)9781450349826

We propose a parallel program representation for heterogeneous systems, designed to enable performance portability across a wide range of popular parallel hardware, including GPUs, vector instruction sets, multicore CPUs and potentially FPGAs. Our representation, which we call HPVM, is a hierarchical dataflow graph with shared memory and vector instructions. HPVM supports three important capabilities for programming heterogeneous systems: a compiler intermediate representation (IR), a virtual instruction set (ISA), and a basis for runtime scheduling;previous systems focus on only one of these capabilities. As a compiler IR, HPVM aims to enable effective code generation and optimization for heterogeneous systems. As a virtual ISA, it can be used to ship executable programs, in order to achieve both functional portability and performance portability across such systems. At runtime, HPVM enables flexible scheduling policies, both through the graph structure and the ability to compile individual nodes in a program to any of the target devices on a system. We have implemented a prototype HPVM system, defining the HPVM IR as an extension of the LLVM compiler IR, compiler optimizations that operate directly on HPVM graphs, and code generators that translate the virtual ISA to NVIDIA GPUs, Intel's AVX vector units, and to multicore X86-64 processors. Experimental results show that HPVM optimizations achieve significant performance improvements, HPVM translators achieve performance competitive with manually developed OpenCL code for both GPUs and vector hardware, and that runtime scheduling policies can make use of both program and runtime information to exploit the flexible compilation capabilities. Overall, we conclude that the HPVM representation is a promising basis for achieving performance portability and for implementing parallelizing compilers for heterogeneous parallel systems.

关键词： Virtual ISA Compiler parallel IR Heterogeneous Systems GPU Vector SIMD

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Interval-Based Memory Reclamation 18

Interval-Based Memory Reclamation

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23rd acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Wen, Haosen Izraelevitz, Joseph Cai, Wentao Beadle, H. Alan Scott, Michael L. Univ Rochester Dept Comp Sci Rochester NY 14627 USA

ISBN: (纸本)9781450349826

In this paper we present interval-based reclamation (IBR), a new approach to safe reclamation of disconnected memory blocks in nonblocking concurrent data structures. Safe reclamation is a difficult problem: a thread, before freeing a block, must ensure that no other threads are accessing that block;the required synchronization tends to be expensive. In contrast with epoch-based reclamation, in which threads reserve all blocks created after a certain time, or pointer-based reclamation (e.g., hazard pointers), in which threads reserve individual blocks, IBR allows a thread to reserve all blocks known to have existed in a bounded interval of time. By comparing a thread's reserved interval with the lifetime of a detached but not yet reclaimed block, the system can determine if the block is safe to free. Like hazard pointers, IBR avoids the possibility that a single stalled thread may reserve an unbounded number of blocks;unlike hazard pointers, it avoids a memory fence on most pointer-following operations. It also avoids the need to explicitly "unreserve" a no-longer-needed pointer. We describe three specific IBR schemes (one with several variants) that trade off performance, applicability, and space requirements. IBR requires no special hardware or OS support. In experiments with data structure microbenchmarks, it also compares favorably (in both time and space) to other state-of-the-art approaches, making it an attractive alternative for libraries of concurrent data structures.

关键词： shared memory garbage collection parallel algorithms

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Griffin: Uniting CPU and GPU in Information Retrieval Systems for Intra-Query parallelism 18

Griffin: Uniting CPU and GPU in Information Retrieval System...

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23rd acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Liu, Yang Wang, Jianguo Swanson, Steven WDC Res Chippenham Wilts England Univ Calif San Diego San Diego CA USA

ISBN: (纸本)9781450349826

Interactive information retrieval services, such as enterprise search and document search, must provide relevant results with consistent, low response times in the face of rapidly growing data sets and query loads. These growing demands have led researchers to consider a wide range of optimizations to reduce response latency, including query processing parallelization and acceleration with co-processors such as GPUs. However, previous work runs queries either on GPU or CPU, ignoring the fact that the best processor for a given query depends on the query's characteristics, which may change as the processing proceeds. We present Griffin, an IR systems that dynamically combines GPU- and CPU-based algorithms to process individual queries according to their characteristics. Griffin uses state-of-the-art CPU-based query processing techniques and incorporates a novel approach to GPU-based query evaluation. Our GPU-based approach, as far as we know, achieves the best available GPU search performance by leveraging a new compression scheme and exploiting an advanced merge-based intersection algorithm. We evaluate Griffin with real world queries and datasets, and show that it improves query performance by 10x compared to a highly optimized CPU-only implementation, and 1.5x compared to our GPU-approach running alone. We also find that Griffin helps reduce the 95th-, 99th-, and 99.9th-percentile query response time by 10.4x, 16.1x, and 26.8x, respectively.

关键词： Information Retrieval Search Engines Query Processing GPU parallel Algorithms

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LazyGraph: Lazy Data Coherency for Replicas in Distributed Graph-parallel Computation 18

LazyGraph: Lazy Data Coherency for Replicas in Distributed G...

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23rd acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Wang, Lei Zhuang, Liangji Chen, Junhang Cui, Huimin Lv, Fang Liu, Ying Fen, Xiaobing Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9781450349826

Replicas of a vertex play an important role in existing distributed graph processing systems which make a single vertex to be parallel processed by multiple machines and access remote neighbors locally without any remote access. However, replicas of vertices introduce data coherency problem. Existing distributed graph systems treat replicas of a vertex v as an atomic and indivisible vertex, and use an eager data coherency approach to guarantee replicas atomicity. In eager data coherency approach, any changes to vertex data must be immediately communicated to all replicas of v, thus leading to frequent global synchronizations and communications. In this paper, we propose a lazy data coherency approach, called LazyAsync, which treats replicas of a vertex as independent vertices and maintains the data coherency by computations, rather than communications in existing eager approach. Our approach automatically selects some data coherency points from the graph algorithm, and maintains all replicas to share the same global view only at such points, which means the replicas are enabled to maintain different local views between any two adjacent data coherency points. Based on PowerGraph, we develop a distributed graph processing system LazyGraph to implement the LazyAsync approach and exploit graph-aware optimizations. On a 48-node EC2-like cluster, LazyGraph outperforms PowerGraph on four widely used graph algorithms across a variety of real-world graphs, with a speedup ranging from 1.25x to 10.69x.

关键词： Lazy Data Coherency Distributed Graphparallel Computation Execution Model

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Proceedings of the acm sigplan symposium on principles and practice of parallel programming, PPOPP

Proceedings of the ACM SIGPLAN Symposium on Principles and P...

引用

20th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2015

ISBN: (纸本)9781450332057

The proceedings contain 44 papers. The topics discussed include: predicate RCU: an RCU for scalable concurrent updates;automatic scalable atomicity via semantic locking;a framework for practical parallel fast matrix multiplication;PLUTO+: near-complete modeling of affine transformations for parallelism and locality;distributed memory code generation for mixed irregular/regular computations;performance implications of dynamic memory allocators on transactional memory systems;low-overhead software transactional memory with progress guarantees and strong semantics∗;barrier elision for production parallel programs;scalable and efficient implementation of 3D unstructured meshes computation: a case study on matrix assembly;and diagnosing the causes and severity of one-sided message contention.

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Certified Compilation of Financial Contracts 18

Certified Compilation of Financial Contracts

引用

20th International symposium on principles and practice of Declarative programming (PPDP)

作者： Annenkov, Danil Elsman, Martin INRIA GALLINETTE Res Ream Nantes France Univ Copenhagen Dept Comp Sci DIKU Copenhagen Denmark

ISBN: (纸本)9781450364416

We present an extension to a certified financial contract management system that allows for templated declarative financial contracts and for integration with financial stochastic models through verified compilation into so-called payoff-expressions. Such expressions readily allow for determining the value of a contract in a given evaluation context, such as contexts created for stochastic simulations. The templating mechanism is useful both at the contract specification level, for writing generic reusable contracts, and for reuse of code that, without the templating mechanism, needs to be recompiled for different evaluation contexts. We report on the effect of using the certified system in the context of a GPGPU-based Monte Carlo simulation engine for pricing various over-the-counter (OTC) financial contracts. The full contract-management system, including the payoff-language compilation, is verified in the Coq proof assistant and certified Haskell code is extracted from our Coq development along with Futhark code for use in a data-parallel pricing engine.

关键词： financial contracts contract languages domain-specific languages certified programming software correctness Coq

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Performance portable C++ programming with RAJA 19

Performance portable C++ programming with RAJA

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Proceedings of the 24th symposium on principles and practice of parallel programming

作者： David Beckingsale Richard Hornung Tom Scogland Arturo Vargas Lawrence Livermore National Laboratory

ISBN: (纸本)9781450362252

With the rapid change of computing architectures, and variety of programming models; the ability to develop performance portable applications has become of great importance. This is particularly true in large production codes where developing and maintaining hardware specific versions is *** simplify the development of performance portable code, we introduce RAJA, our C++ library that allows developers to write single-source applications that can target multiple hardware and programming model back-ends. We provide a thorough introduction to all of RAJA features, and walk through some hands-on examples that will allow attendees to understand how RAJA might benefit their own applications. Attendees should bring a laptop computer to participate in the hands-on *** tutorial will introduce attendees to RAJA, a C++ library for developing performance portable applications. Attendees will learn how to write performance portable code that can execute on a range of programming models (OpenMP, CUDA, Intel TBB, and HCC) and hardware (CPU, GPU, Xeon Phi).Specifically, attendees will learn how to convert existing C++ applications to use RAJA, and how to use RAJA's programming abstractions to expose existing parallelism in their applications without complex algorithm rewrites. We will also cover specific guidelines for using RAJA in a large application, including some common "gotchas" and how to handle memory management. Finally, attendees will learn how to categorize loops to allow for simple and systematic performance tuning on any architecture.

关键词： parallel programming

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An Architecture and programming Model for Accelerating parallel Commutative Computations via Privatization 22

An Architecture and Programming Model for Accelerating Paral...

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22nd acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Balaji, Vignesh Tirumala, Dhruva Lucia, Brandon Carnegie Mellon Univ Pittsburgh PA 15213 USA

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Recovering Performance for Vector-based Machine Learning on Managed Runtime 22

Recovering Performance for Vector-based Machine Learning on ...

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22nd acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Wu, Mingyu Guan, Haibing Zang, Binyu Chen, Haibo Shanghai Jiao Tong Univ Inst Parallel & Distributed Syst Shanghai Key Lab Scalable Comp & Syst Shanghai Peoples R China

ISBN: (纸本)9781450344937

The explosive growth of data and the demand for learning useful information from such data have stimulated a crossdisciplinary area named big learning, which leverages a cluster of commodity machines to run machine learning applications on large datasets. Those applications are usually implemented on high-level programming frameworks [1-4], which are running atop managed runtimes. Since the applications usually involve many iterations of computation over input data, the frameworks will cache them for performance consideration. In this work, we investigate a set of vectorbased machine learning applications in Spark MLlib [3] and find that cached datasets have a strong impact on overall efficiency. Copyright is held by the Owner/Author(s).

关键词： Learning systems

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Using Butterfly-Patterned Partial Sums to Draw from Discrete Distributions 17

Using Butterfly-Patterned Partial Sums to Draw from Discrete...

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22nd acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Steele, Guy L., Jr. Tristan, Jean-Baptiste Oracle Labs Ludhiana Punjab India

ISBN: (纸本)9781450344937

We describe a SIMD technique for drawing values from multiple discrete distributions, such as sampling from the random variables of a mixture model, that avoids computing a complete table of partial sums of the relative probabilities. A table of alternate ("butterfly-patterned") form is faster to compute, making better use of coalesced memory accesses;from this table, complete partial sums are computed on the fly during a binary search. Measurements using CUBA 7.5 on an NVIDIA Titan Black GPU show that this technique makes an entire machine-learning application that uses a Latent Dirichlet Allocation topic model with 1024 topics about about 13% faster (when using single-precision floating-point data) or about 35% faster (when using double precision floating-point data) than doing a straightforward matrix transposition after using coalesced accesses.

关键词： butterfly coalesced memory access discrete distribution GPU latent Dirichlet allocation LDA machine learning multithreading memory bottleneck parallel computing random sampling SIMD transposed memory access

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