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9th acm sigplan symposium on principles and practice of parallel programming

作者： Liu, T Martonosi, M Princeton Univ Dept Comp Sci Princeton NJ 08544 USA Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)9781581135886

Sensor networks are long-running computer systems with many sensing/compute nodes working to gather information about their environment, process and fuse that information, and in some cases, actuate control mechanisms in response. Like traditional parallel systems, communication between nodes is of fundamental importance, but is typically accomplished via wireless transceivers. One further key attribute of sensor networks is that they are almost always long-running systems, intended to operate in situ, with minimal direct human intervention, for months or years. This requirement for long-running autonomy mandates careful design of the runtime system that manages applications on each node, to ensure reliability and ease of upgrades over the life of the system. This paper describes Impala, a middleware architecture that enables application modularity, adaptivity, and repair-ability in wireless sensor networks. Impala allows software updates to be received via the node's wireless transceiver and to be applied to the running system dynamically. In addition, Impala also provides an interface for on-the-fly application adaptation in order to improve the performance, energy-efficiency, and reliability of the software system. Impala has been designed to be a part of the ZebraNet mobile sensor network, but we are also prototyping it within HP/Compaq iPAQ Pocket PC handhelds. We present performance data for both real system measurements of the Pocket PC version as well as simulations of a full mobile sensor system deployment. Overall, Impala is a lightweight runtime system that can greatly improve system reliability, performance, and energy-efficiency. The ideas introduced here for sensor networks have applicability more broadly in other long-running autonomous parallel systems as well.

关键词： design experimentation performance sensor networks middleware system software adaptation software update

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Leveraging parallel Nesting in Transactional Memory

Leveraging Parallel Nesting in Transactional Memory

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Barreto, Joao Dragojevic, Aleksandar Ferreira, Paulo Guerraoui, Rachid Kapalka, Michal Univ Tecn Lisboa INESC ID Lisbon Portugal Swiss Fed Inst Technol CH-1015 Lausanne Switzerland

ISBN: (纸本)9781605587080

Exploiting the emerging reality of affordable multi-core architectures goes through providing programmers with simple abstractions that would enable them to easily turn their sequential programs into concurrent ones that expose as much parallelism as possible. While transactional memory promises to make concurrent programming easy to a wide programmer community, current implementations either disallow nested transactions to run in parallel or do not scale to arbitrary parallel nesting depths. This is an important obstacle to the central goal of transactional memory, as programmers can only start parallel threads in restricted parts of their code. This paper addresses the intrinsic difficulty behind the support for parallel nesting in transactional memory, and proposes a novel solution that, to the best of our knowledge, is the first practical solution to meet the lowest theoretical upper bound known for the problem. Using a synthetic workload configured to test parallel transactions on a multi-core machine, a practical implementation of our algorithm yields substantial speed-ups (up to 22x with 33 threads) relatively to serial nesting, and shows that the time to start and commit transactions, as well as to detect conflicts, is independent of nesting depth.

关键词： Algorithms Nested parallel programs fork-join work-stealing transactional memory

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Communication-Avoiding parallel Minimum Cuts and Connected Components 18

Communication-Avoiding Parallel Minimum Cuts and Connected C...

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23rd acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Gianinazzi, Lukas Kalvoda, Pavel De Palma, Alessandro Besta, Maciej Hoefler, Torsten Swiss Fed Inst Technol Dept Comp Sci Zurich Switzerland Google Inc Mountain View CA USA

ISBN: (纸本)9781450349826

We present novel scalable parallel algorithms for finding global minimum cuts and connected components, which are important and fundamental problems in graph processing. To take advantage of future massively parallel architectures, our algorithms are communication-avoiding: they reduce the costs of communication across the network and the cache hierarchy. The fundamental technique underlying our work is the randomized sparsification of a graph: removing a fraction of graph edges, deriving a solution for such a sparsified graph, and using the result to obtain a solution for the original input. We design and implement sparsification with O(1) synchronization steps. Our global minimum cut algorithm decreases communication costs and computation compared to the state-of-the-art, while our connected components algorithm incurs few cache misses and synchronization steps. We validate our approach by evaluating MPI implementations of the algorithms on a petascale supercomputer. We also provide an approximate variant of the minimum cut algorithm and show that it approximates the exact solutions well while using a fraction of cores in a fraction of time.

关键词： parallel Computing Minimum cuts Randomized Algorithms Graph Algorithms

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A Comparison of programming Models for Multiprocessors with Explicitly Managed Memory Hierarchies

A Comparison of Programming Models for Multiprocessors with ...

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14th acm sigplan symposium on principles and practice of parallel programming

作者： Schneider, Scott Yeom, Jae-Seung Rose, Benjamin Linford, John C. Sandu, Adrian Nikolopoulos, Dimitrios S. Virginia Tech Dept Comp Sci Blacksburg VA 24060 USA

ISBN: (纸本)9781605583976

On multiprocessors with explicitly managed memory hierarchies (EMM), software has the responsibility of moving data in and out of fast local memories. This task can be complex and error-prone even for expert programmers. Before we can allow compilers to handle the complexity for us, we must identify the abstractions that are general enough to allow us to write applications with reasonable effort, yet specific enough to exploit the vast on-chip memory bandwidth of EMM multi-processors. To this end, we compare two programming models against hand-tuned codes on the STI Cell, paying attention to programmability and performance. The first programming model, Sequoia, abstracts the memory hierarchy as private address spaces, each corresponding to a parallel task. The second, Cellgen, is a new framework which provides OpenMP-like semantics and the abstraction of a shared address spaces divided into private and shared data. We compare three applications programmed using these models against their hand-optimized counterparts in terms of abstractions, programming complexity, and performance.

关键词： Design Languages Cell BE Explicitly Managed Memory Hierarchies programming Models

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Extracting logical structure and identifying stragglers in parallel execution traces 14

Extracting logical structure and identifying stragglers in p...

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2014 19th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2014

作者： Isaacs, Katherine E. Gamblin, Todd Bhatele, Abhinav Bremer, Peer-Timo Schulz, Martin Hamann, Bernd Department of Computer Science University of California Davis United States Center for Applied Scientific Computing Lawrence Livermore National Laboratory United States

ISBN: (纸本)9781450326568

We introduce a new approach to automatically extract an idealized logical structure from a parallel execution trace. We use this structure to define intuitive metrics such as the lateness of a process involved in a parallel execution. By analyzing and illustrating traces in terms of logical steps, we leverage a developer's understanding of the happened-before relations in a parallel program. This technique can uncover dependency chains, elucidate communication patterns, and highlight sources and propagation of delays, all of which may be obscured in a traditional trace visualization.

关键词： Visualization

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Correct and efficient work-stealing for weak memory models 13

Correct and efficient work-stealing for weak memory models

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18th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2013

作者： Lê, Nhat Minh Pop, Antoniu Cohen, Albert Zappa Nardelli, Francesco INRIA ENS Paris Paris France

ISBN: (纸本)9781450319225

Chase and Lev's concurrent deque is a key data structure in shared-memory parallel programming and plays an essential role in work-stealing schedulers. We provide the first correctness proof of an optimized implementation of Chase and Lev's deque on top of the POWER and ARM architectures: these provide very relaxed memory models, which we exploit to improve performance but considerably complicate the reasoning. We also study an optimized x86 and a portable C11 implementation, conducting systematic experiments to evaluate the impact of memory barrier optimizations. Our results demonstrate the benefits of hand tuning the deque code when running on top of relaxed memory models. © 2013 acm.

关键词： parallel programming

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Data Transformations Enabling Loop Vectorization on Multithreaded Data parallel Architectures

Data Transformations Enabling Loop Vectorization on Multithr...

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Jang, Byunghyun Mistry, Perhaad Schaa, Dana Dominguez, Rodrigo Kaeli, David Northeastern Univ Dept ECE Boston MA 02115 USA

ISBN: (纸本)9781605587080

Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memory access patterns in the data stream. This paper describes data transformations that allow us to vectorize loops targeting massively multithreaded data parallel architectures. We present a mathematical model that captures loop-based memory access patterns and computes the most appropriate data transformations in order to enable vectorization. Our experimental results show that the proposed data transformations can significantly increase the number of loops that can be vectorized and enhance the data-level parallelism of applications. Our results also show that the overhead associated with our data transformations can be easily amortized as the size of the input data set increases. For the set of high performance benchmark kernels studied, we achieve consistent and significant performance improvements (up to 11.4X) by applying vectorization using our data transformation approach.

关键词： Loop Vectorization Data Transformation GPGPU

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Automatic Formal Verification of MPI-Based parallel Programs 11

Automatic Formal Verification of MPI-Based Parallel Programs

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16th acm symposium on principles and practice of parallel programming

作者： Siegel, Stephen F. Zirkel, Timothy K. Univ Delaware Verified Software Lab Dept Comp & Informat Sci Newark DE 19716 USA

ISBN: (纸本)9781450301190

The Toolkit for Accurate Scientific Software (TASS) is a suite of tools for the formal verification of MPI-based parallel programs used in computational science. TASS can verify various safety properties as well as compare two programs for functional equivalence. The TASS front end takes an integer n >= 1 and a C/MPI program, and constructs an abstract model of the program with n processes. Procedures, structs, (multi-dimensional) arrays, heap-allocated data, pointers, and pointer arithmetic are all representable in a TASS model. The model is then explored using symbolic execution and explicit state space enumeration. A number of techniques are used to reduce the time and memory consumed. A variety of realistic MPI programs have been verified with TASS, including Jacobi iteration and manager-worker type programs, and some subtle defects have been discovered. TASS is written in Java and is available from http://***/tass under the Gnu Public License.

关键词： Verification Symbolic execution MPI message-passing debugging verification

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parallel 'go with the winners' algorithms in distributed memory models

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JOURNAL OF parallel AND DISTRIBUTED COMPUTING 2003年第9期63卷 801-814页

作者： Peinado, M Lengauer, T Microsoft Corp Redmond WA 98052 USA Max Planck Inst Comp Sci D-66123 Saarbrucken Germany

We parallelize the 'go with the winners' algorithm of Aldous and Vazirani (in: Proceedings of the 35th IEEE symposium on the Foundations of Computer Science, IEEE Computer Society Press, Silver Spring., MD, 1994, pp. 492-501) and analyze the resulting parallel algorithm in the LogP-model (in: Proceedings of the Fourth acm sigplan symposium on principles & practice of parallel programming, 1993, pp. 1-12). The main issues in the analysis are load imbalances and communication delays. The result of the analysis is a practical algorithm which, under reasonable assumptions, achieves linear speedup. Finally, we analyze our algorithm for a concrete application: generating models of amorphous chemical structures. (C) 2003 Elsevier Inc. All rights reserved.

关键词： parallel algorithms go with the winners LogP model second moment method load balancing amorphous solids self-avoiding walks

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Work-stealing with Configurable Scheduling Strategies 13

Work-stealing with Configurable Scheduling Strategies

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18th acm sigplan symposium on principles and practice of parallel programming

作者： Wimmer, Martin Traeff, Jesper Larsson Cederman, Daniel Tsigas, Philippas Vienna Univ Technol Fac Informat Res Grp Parallel Comp A-1040 Vienna Austria Chalmers Univ Technol S-41296 Gothenburg Sweden

ISBN: (纸本)9781450319225

Work-stealing systems are typically oblivious to the nature of the tasks they are scheduling. They do not know or take into account how long a task will take to execute or how many subtasks it will spawn. Moreover, task execution order is typically determined by an underlying task storage data structure, and cannot be changed. There are thus possibilities for optimizing task parallel executions by providing information on specific tasks and their preferred execution order to the scheduling system. We investigate generalizations of work-stealing and introduce a framework enabling applications to dynamically provide hints on the nature of specific tasks using scheduling strategies. Strategies can be used to independently control both local task execution and steal order. Strategies allow optimizations on specific tasks, in contrast to more conventional scheduling policies that are typically global in scope. Strategies are composable and allow different, specific scheduling choices for different parts of an application simultaneously. We have implemented a work-stealing system based on our strategy framework. A series of benchmarks demonstrates beneficial effects that can be achieved with scheduling strategies.

关键词： Algorithms Work-stealing scheduler hints strategies priorities

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