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检索条件"任意字段=2003 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming"

共 560 条记录，以下是271-280 订阅

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The Pilot Library for Novice MPI Programmers

The Pilot Library for Novice MPI Programmers

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Carter, John D. Gardner, William B. Grewal, Gary Univ Guelph Sch Comp Sci Guelph ON N1G 2W1 Canada

ISBN: (纸本)9781605587080

The Pilot library is a new method for programming MPI-enabled clusters in C, targeted at novice parallel programmers. Formal elements from Communicating Sequential Processes (CSP) are used to realize a process/channel model of parallel computation that reduces opportunities for deadlock and other communication errors. This simple model, plus an application programming interface (API) styled after C's formatted I/O, are designed to make the library easy to learn. The Pilot library exists as a thin layer on top of any standard Message Passing Interface (MPI) implementation, preserving MPI's portability and efficiency, with little performance overhead arising as result of Pilot's additional features.

关键词： Design Languages high-performance computing cluster programming C MPI collective operations deadlock detection

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Structure-driven Optimizations for Amorphous Data-parallel Programs

Structure-driven Optimizations for Amorphous Data-parallel P...

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Mendez-Lojo, Mario Nguyen, Donald Prountzos, Dimitrios Sui, Xin Hassaan, M. Amber Kulkarni, Milind Burtscher, Martin Pingali, Keshav Univ Texas Austin Inst Computat Engn & Sci Austin TX 78712 USA

ISBN: (纸本)9781605587080

Irregular algorithms are organized around pointer-based data structures such as graphs and trees, and they are ubiquitous in applications. Recent work by the Galois project has provided a systematic approach for parallelizing irregular applications based on the idea of optimistic or speculative execution of programs. However, the overhead of optimistic parallel execution can be substantial. In this paper, we show that many irregular algorithms have structure that can be exploited and present three key optimizations that take advantage of algorithmic structure to reduce speculative overheads. We describe the implementation of these optimizations in the Galois system and present experimental results to demonstrate their benefits. To the best of our knowledge, this is the first system to exploit algorithmic structure to optimize the execution of irregular programs.

关键词： Amorphous Data-parallelism Irregular Programs Optimistic parallelization Synchronization Overheads Cautious Operator Implementations One-shot Optimization Iteration Coalescing

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Load Balancing on Speed

Load Balancing on Speed

引用

15th acm sigplan symposium on principles and practice of parallel programming

作者： Hofmeyr, Steven Iancu, Costin Blagojevic, Filip Lawrence Berkeley Natl Lab Berkeley CA USA

ISBN: (纸本)9781605587080

To fully exploit multicore processors, applications are expected to provide a large degree of thread-level parallelism. While adequate for low core counts and their typical workloads, the current load balancing support in operating systems may not be able to achieve efficient hardware utilization for parallel workloads. Balancing run queue length globally ignores the needs of parallel applications where threads are required to make equal progress. In this paper we present a load balancing technique designed specifically for parallel applications running on multicore systems. Instead of balancing run queue length, our algorithm balances the time a thread has executed on "faster" and "slower" cores. We provide a user level implementation of speed balancing on UMA and NUMA multi-socket architectures running Linux and discuss behavior across a variety of workloads, usage scenarios and programming models. Our results indicate that speed balancing when compared to the native Linux load balancing improves performance and provides good performance isolation in all cases considered. Speed balancing is also able to provide comparable or better performance than DWRR, a fair multi-processor scheduling implementation inside the Linux kernel. Furthermore, parallel application performance is often determined by the implementation of synchronization operations and speed balancing alleviates the need for tuning the implementations of such primitives.

关键词： Experimentation Theory Performance Measurement Languages Design parallel programming Operating System Load Balancing Speed Balancing Multicore Multisocket

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Data Transformations Enabling Loop Vectorization on Multithreaded Data parallel Architectures

Data Transformations Enabling Loop Vectorization on Multithr...

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Jang, Byunghyun Mistry, Perhaad Schaa, Dana Dominguez, Rodrigo Kaeli, David Northeastern Univ Dept ECE Boston MA 02115 USA

ISBN: (纸本)9781605587080

Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memory access patterns in the data stream. This paper describes data transformations that allow us to vectorize loops targeting massively multithreaded data parallel architectures. We present a mathematical model that captures loop-based memory access patterns and computes the most appropriate data transformations in order to enable vectorization. Our experimental results show that the proposed data transformations can significantly increase the number of loops that can be vectorized and enhance the data-level parallelism of applications. Our results also show that the overhead associated with our data transformations can be easily amortized as the size of the input data set increases. For the set of high performance benchmark kernels studied, we achieve consistent and significant performance improvements (up to 11.4X) by applying vectorization using our data transformation approach.

关键词： Loop Vectorization Data Transformation GPGPU

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Effective Communication and Computation Overlap with Hybrid MPI/SMPSs

Effective Communication and Computation Overlap with Hybrid ...

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Marjanovic, Vladimir Labarta, Jesus Ayguade, Eduard Valero, Mateo Barcelona Supercomp Ctr BSC CNS Dept Comp Sci Barcelona Spain Tech Univ Catalunya UPC Comp Architecture Dept Barcelona Spain

ISBN: (纸本)9781605587080

Communication overhead is one of the dominant factors affecting performance in high-performance computing systems. To reduce the negative impact of communication, programmers overlap communication and computation by using asynchronous communication primitives. This increases code complexity, requiring more development effort and making less readable programs. This paper presents the hybrid use of MPI and SMPSs (SMP superscalar, a task-based shared-memory programming model) that allows the programmer to easily introduce the asynchrony necessary to overlap communication and computation. We demonstrate the hybrid use of MPI/SMPSs with the high-performance LINPACK benchmark (HPL), and compare it to the pure MPI implementation, which uses the look-ahead technique to overlap communication and computation. The hybrid MPI/SMPSs version significantly improves the performance of the pure MPI version, getting close to the asymptotic performance at medium problem sizes and still getting significant benefits at small/large problem sizes.

关键词： Algorithms Performance Languages parallel programming model MPI hybrid MPI/SMPSs LINPACK

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Is Transactional programming Actually Easier?

Is Transactional Programming Actually Easier?

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Rossbach, Christopher J. Hofmann, Owen S. Witchel, Emmett Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781605587080

Chip multi-processors (CMPs) have become ubiquitous, while tools that ease concurrent programming have not. The promise of increased performance for all applications through ever more parallel hardware requires good tools for concurrent programming, especially for average programmers. Transactional memory (TM) has enjoyed recent interest as a tool that can help programmers program concurrently. The transactional memory (TM) research community is heavily invested in the claim that programming with transactional memory is easier than alternatives (like locks), but evidence for or against the veracity of this claim is scant. In this paper, we describe a user-study in which 237 undergraduate students in an operating systems course implement the same programs using coarse and fine-grain locks, monitors, and transactions. We surveyed the students after the assignment, and examined their code to determine the types and frequency of programming errors for each synchronization technique. Inexperienced programmers found baroque syntax a barrier to entry for transactional programming. On average, subjective evaluation showed that students found transactions harder to use than coarse-grain locks, but slightly easier to use than fine-grained locks. Detailed examination of synchronization errors in the students' code tells a rather different story. Overwhelmingly, the number and types of programming errors the students made was much lower for transactions than for locks. On a similar programming problem, over 70% of students made errors with fine-grained locking, while less than 10% made errors with transactions.

关键词： Design Performance Transactional Memory Optimistic Concurrency Synchronization

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Scaling LAPACK Panel Operations Using parallel Cache Assignment

Scaling LAPACK Panel Operations Using Parallel Cache Assignm...

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Castaldo, Anthony M. Whaley, R. Clint Univ Texas San Antonio Dept Comp Sci San Antonio TX 78249 USA

ISBN: (纸本)9781605587080

In LAPACK many matrix operations are cast as block algorithms which iteratively process a panel using an unblocked algorithm and then update a remainder matrix using the high performance Level 3 BLAS. The Level 3 BLAS have excellent weak scaling, but panel processing tends to be bus bound, and thus scales with bus speed rather than the number of processors (p). Amdahl's law therefore ensures that as p grows, the panel computation will become the dominant cost of these LAPACK routines. Our contribution is a novel parallel cache assignment approach which we show scales well with p. We apply this general approach to the QR and LU panel factorizations on two commodity 8-core platforms with very different cache structures, and demonstrate superlinear panel factorization speedups on both machines. Other approaches to this problem demand complicated reformulations of the computational approach, new kernels to be tuned, new mathematics, an inflation of the high-order flop count, and do not perform as well. By demonstrating a straight-forward alternative that avoids all of these contortions and scales with p, we address a critical stumbling block for dense linear algebra in the age of massive parallelism.

关键词： ATLAS LAPACK QR LU factorization parallel multicore multi-core GPU

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Leveraging parallel Nesting in Transactional Memory

Leveraging Parallel Nesting in Transactional Memory

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Barreto, Joao Dragojevic, Aleksandar Ferreira, Paulo Guerraoui, Rachid Kapalka, Michal Univ Tecn Lisboa INESC ID Lisbon Portugal Swiss Fed Inst Technol CH-1015 Lausanne Switzerland

ISBN: (纸本)9781605587080

Exploiting the emerging reality of affordable multi-core architectures goes through providing programmers with simple abstractions that would enable them to easily turn their sequential programs into concurrent ones that expose as much parallelism as possible. While transactional memory promises to make concurrent programming easy to a wide programmer community, current implementations either disallow nested transactions to run in parallel or do not scale to arbitrary parallel nesting depths. This is an important obstacle to the central goal of transactional memory, as programmers can only start parallel threads in restricted parts of their code. This paper addresses the intrinsic difficulty behind the support for parallel nesting in transactional memory, and proposes a novel solution that, to the best of our knowledge, is the first practical solution to meet the lowest theoretical upper bound known for the problem. Using a synthetic workload configured to test parallel transactions on a multi-core machine, a practical implementation of our algorithm yields substantial speed-ups (up to 22x with 33 threads) relatively to serial nesting, and shows that the time to start and commit transactions, as well as to detect conflicts, is independent of nesting depth.

关键词： Algorithms Nested parallel programs fork-join work-stealing transactional memory

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Using Data Structure Knowledge for Efficient Lock Generation and Strong Atomicity

Using Data Structure Knowledge for Efficient Lock Generation...

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Upadhyaya, Gautam Midkiff, Samuel P. Pai, Vijay S. Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9781605587080

To achieve high-performance on multicore systems, shared-memory parallel languages must efficiently implement atomic operations. The commonly used and studied paradigms for atomicity are fine-grained locking, which is both difficult to program and error-prone;optimistic software transactions, which require substantial overhead to detect and recover from atomicity violations;and compiler-generation of locks from programmer-specified atomic sections, which leads to serialization whenever imprecise pointer analysis suggests the mere possibility of a conflicting operation. This paper presents a new strategy for compiler-generated locking that uses data structure knowledge to facilitate more precise alias and lock generation analyses and reduce unnecessary serialization. Implementing and evaluating these ideas in the Java language shows that the new strategy achieves eight-thread speedups of 0.83 to 5.9 for the five STAMP benchmarks studied, outperforming software transactions on all but one benchmark, and nearly matching programmer-specified fine-grained locks on all but one benchmark. The results also indicate that compiler knowledge of data structures improves the effectiveness of compiler analysis, boosting eight-thread performance by up to 300%. Further, the new analysis allows for software support of strong atomicity with less than 1% overhead for two benchmarks and less than 20% for three others. The strategy also nearly matches the performance of programmer-specified fine-grained locks for the SPECjbb2000 benchmark, which has traditionally not been amenable to static analyses.

关键词： Algorithms Performance Design Automatic lock generation transactional memory parallel programming

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An Adaptive Performance Modeling Tool for GPU Architectures

An Adaptive Performance Modeling Tool for GPU Architectures

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15th acm sigplan symposium on principles and practice of parallel programming

作者： Baghsorkhi, Sara S. Delahaye, Matthieu Patel, Sanjay J. Gropp, William D. Hwu, Wen-mei W. Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9781605587080

This paper presents an analytical model to predict the performance of general-purpose applications on a GPU architecture. The model is designed to provide performance information to an auto-tuning compiler and assist it in narrowing down the search to the more promising implementations. It can also be incorporated into a tool to help programmers better assess the performance bottlenecks in their code. We analyze each GPU kernel and identify how the kernel exercises major GPU microarchitecture features. To identify the performance bottlenecks accurately, we introduce an abstract interpretation of a GPU kernel, work flow graph, based on which we estimate the execution time of a GPU kernel. We validated our performance model on the NVIDIA GPUs using CUDA (Compute Unified Device Architecture). For this purpose, we used data parallel benchmarks that stress different GPU microarchitecture events such as uncoalesced memory accesses, scratch-pad memory bank conflicts, and control flow divergence, which must be accurately modeled but represent challenges to the analytical performance models. The proposed model captures full system complexity and shows high accuracy in predicting the performance trends of different optimized kernel implementations. We also describe our approach to extracting the performance model automatically from a kernel code.

关键词： Design Measurement Performance Analytical model GPU parallel programming Performance estimation

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