检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

510 篇 会议
49 篇 期刊文献
1 册 图书

馆藏范围

560 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

464 篇 工学
- 413 篇 软件工程
- 359 篇 计算机科学与技术...
- 21 篇 电子科学与技术（可...
- 21 篇 控制科学与工程
- 9 篇 信息与通信工程
- 5 篇 机械工程
- 4 篇 电气工程
- 4 篇 生物工程
- 3 篇 动力工程及工程热...
- 3 篇 生物医学工程（可授...
- 2 篇 力学（可授工学、理...
- 2 篇 建筑学
- 2 篇 土木工程
- 2 篇 农业工程
- 1 篇 冶金工程
87 篇 理学
- 78 篇 数学
- 12 篇 系统科学
- 7 篇 统计学（可授理学、...
- 4 篇 生物学
- 2 篇 物理学
- 2 篇 化学
- 1 篇 大气科学
- 1 篇 地质学
26 篇 管理学
- 19 篇 管理科学与工程(可...
- 14 篇 工商管理
- 7 篇 图书情报与档案管...
3 篇 经济学
- 3 篇 应用经济学
3 篇 法学
- 3 篇 社会学
2 篇 教育学
- 2 篇 教育学
2 篇 农学
- 2 篇 作物学

主题

74 篇 performance
72 篇 parallel process...
62 篇 parallel program...
44 篇 algorithms
42 篇 languages
35 篇 design
26 篇 parallel algorit...
25 篇 gpu
14 篇 computer program...
13 篇 parallel computi...
13 篇 parallel
12 篇 experimentation
12 篇 measurement
10 篇 mpi
10 篇 transactional me...
9 篇 graphics process...
9 篇 theory
9 篇 concurrency
8 篇 synchronization
7 篇 multithreading

机构

13 篇 carnegie mellon ...
7 篇 indiana univ blo...
4 篇 univ wisconsin d...
4 篇 univ chinese aca...
4 篇 univ illinois ur...
4 篇 swiss fed inst t...
4 篇 mit csail united...
4 篇 shanghai jiao to...
4 篇 mit comp sci & a...
4 篇 rice university
4 篇 univ rochester r...
4 篇 purdue univ w la...
3 篇 univ of tokyo
3 篇 tsinghua univ de...
3 篇 massachusetts in...
3 篇 ohio state univ ...
3 篇 carnegie mellon ...
3 篇 inria rocquencou...
3 篇 itmo univ st pet...
3 篇 tsinghua univ pe...

作者

9 篇 chen haibo
8 篇 hoefler torsten
8 篇 blelloch guy e.
8 篇 agrawal kunal
7 篇 garland michael
7 篇 leiserson charle...
6 篇 sun yihan
6 篇 zhai jidong
6 篇 shun julian
6 篇 mellor-crummey j...
5 篇 rainey mike
5 篇 miller barton p.
5 篇 krishnamoorthy s...
5 篇 tsigas philippas
5 篇 padua david
5 篇 nikolopoulos dim...
5 篇 lam monica s.
5 篇 valero mateo
5 篇 scott michael l.
4 篇 taura kenjiro

语言

521 篇 英文
39 篇 其他

检索条件"任意字段=2003 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming"

共 560 条记录，以下是331-340 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A Case Study in SIMD Text Processing with parallel Bit Streams UTF-8 to UTF-16 Transcoding 08

A Case Study in SIMD Text Processing with Parallel Bit Strea...

引用

acm sigplan symposium on principles and practice of parallel programming (PPoPP 08)

作者： Cameron, Robert D. Simon Fraser Univ Sch Comp Sci Burnaby BC V5A 1S6 Canada

ISBN: (纸本)9781595939609

High performance SIMD text processing using the method of parallel bit streams is introduced with a case study of UTF-8 to UTF-16 transcoding. A forward transform converts byte-oriented character stream data into eight parallel bit streams. Decoding, validation and computation of UTF-8 indexed UTF-16 bit streams are performed using bit-parallel logic and shifting operations. Conversion from UTF-8 indexing to UTF-16 indexing is performed using parallel bit deletion. The inverse transform is applied to yield high and low UTF-16 byte streams which are then merged. Combined with optimization techniques for blocks of ASCII data, speed-ups of 3 to 25 times are achieved on commodity processors compared with optimized byte-at-a-time code. Further applications of the method of parallel bit streams to bulk text processing applications are briefly discussed along with future prospects for the combination of intraregister and intrachip parallelism on multicore processors.

关键词： SIMD text processing parallel bit streams UTF-8 UTF-16 transcoding

来源：评论

学校读者我要写书评

暂无评论

Performance without Pain = Productivity Data Layout and Collective Communication in UPC 08

Performance without Pain = Productivity Data Layout and Coll...

引用

acm sigplan symposium on principles and practice of parallel programming (PPoPP 08)

作者： Nishtala, Rajesh Almasi, George Cascaval, Calin Univ Calif Berkeley Div Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781595939609

The next generations of supercomputers are projected to have hundreds of thousands of processors. However, as the numbers of processors grow, the scalability of applications will be the dominant challenge. This forces us to reexamine some of our fundamental ways that we approach the design and use of parallel languages and runtime systems. In this paper we show how the globally shared arrays in a popular Partitioned Global Address Space (PGAS) language, Unified parallel C (UPC), can be combined with a new collective interface to improve both performance and scalability. This interface allows subsets, or teams, of threads to perform a collective together. As opposed to MPI's communicators, our interface allows set of threads to be placed in teams instantly rather than explicitly constructing communicators, thus allowing for a more dynamic team construction and manipulation. We motivate our ideas with three application kernels: Dense Matrix Multiplication, Dense Cholesky factorization and multidimensional Fourier transforms. We describe how the three aforementioned applications can be succinctly written in UPC thereby aiding productivity. We also show how such an interface allows for scalability by running on up to 16,384 processors on the BlueGene/L. In a few lines of UPC code, we wrote a dense matrix multiply routine achieves 28.8 TFlop/s and a 3D FFT that achieves 2.1 TFlop/s. We analyze our performance results through models and show that the machine resources rather than the interfaces themselves limit the performance.

关键词： Blue Gene Collective Communication PGAS parallel programming programming Productivity UPC

来源：评论

学校读者我要写书评

暂无评论

Towards execution time estimation in abstract machine-based languages 08

Towards execution time estimation in abstract machine-based ...

引用

PPDP 2008: 10th International acm sigplan symposium on principles and practice of Declarative programming

作者： Mera, E. Lopez, P. Carro, M. Hermenegildo, M. Complutense University of Madrid IMDEA Software Technical U. of Madrid U. of New Mexico

ISBN: (纸本)9781605581170

Abstract machines provide a certain separation between platform-dependent and platform-independent concerns in compilation. Many of the differences between architectures are encapsulated in the specific abstract machine implementation and the bytecode is left largely architecture independent. Taking advantage of this fact, we present a framework for estimating upper and lower bounds on the execution times of logic programs running on a bytecode-based abstract machine. Our approach includes a one-time, program-independent profiling stage which calculates constants or functions bounding the execution time of each abstract machine instruction. Then, a compile-time cost estimation phase, using the instruction timing information, infers expressions giving platform-dependent upper and lower bounds on actual execution time as functions of input data sizes for each program. Working at the abstract machine level makes it possible to take into account low-level issues in new architectures and platforms by just reexecuting the calibration stage instead of having to tailor the analysis for each architecture and platform. Applications of such predicted execution times include debugging/verification of time properties, certification of time properties in mobile code, granularity control in parallel/distributed computing, and resource-oriented specialization. Copyright © 2008 acm.

关键词： Logic programming

来源：评论

学校读者我要写书评

暂无评论

programming with tiles

Programming with tiles

引用

作者： Guo, Jia Bikshandit, Ganesh Fraguela, Basilio B. Garzarán, María J. Padua, David University of Illinois Urbana-Champaign IL United States IBM India Universidade da Coruña Spain

ISBN: (纸本)9781595939609

The importance of tiles or blocks in scientific computing cannot be overstated. Many algorithms, both iterative and recursive, can be expressed naturally if tiles are represented explicitly. From the point of view of performance, tiling, either as a code or a data layout transformation, is one of the most effective ways to exploit locality, which is a must to achieve good performance in current computers because of the significant difference in speed between processor and memory. Furthermore, tiles are also useful to express data distribution in parallel computations. However, despite the importance of tiles, most languages do not support them directly. This gives place to bloated programs populated with numerous subscript expressions which make the code difficult to read and coding mistakes more likely. This paper discusses Hierarchically Tiled Arrays (HTAs), a data type which facilitates the easy manipulation of tiles in objectoriented languages with emphasis on two new features, dynamic partitioning and overlapped tiling. These features facilitate the expression of locality and communication while maintaining the same performance of algorithms written using conventional languages. Copyright © 2008 acm.

关键词： parallel programming

来源：评论

学校读者我要写书评

暂无评论

A case study in SIMD text processing with parallel bit streams UTF-8 to UTF-16 transcoding

A case study in SIMD text processing with parallel bit strea...

引用

作者： Cameron, Robert D. School of Computing Science Simon Fraser University Canada

ISBN: (纸本)9781595939609

关键词： Text processing

来源：评论

学校读者我要写书评

暂无评论

Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories

Automatic data movement and computation mapping for multi-le...

引用

作者： Baskaran, Muthu Manikandan Ramanujam, J. Bondhugula, Uday Rountev, Atanas Krishnamoorthy, Sriram Sadayappan, P. Dept. of Computer Science and Engineering Ohio State University 2015 Neil Ave Columbus OH United States Dept. of Electrical and Computer Engg Center for Computation and Technology Louisiana State University United States

ISBN: (纸本)9781595939609

Several parallel architectures such as GPUs and the Cell processor have fast explicitly managed on-chip memories, in addition to slow off-chip memory. They also have very high computational power with multiple levels of parallelism. A significant challenge in programming these architectures is to effectively exploit the parallelism available in the architecture and manage the fast memories to maximize performance. In this paper we develop an approach to effective automatic data management for on-chip memories, including creation of buffers in on-chip (local) memories for holding portions of data accessed in a computational block, automatic determination of array access functions of local buffer references, and generation of code that moves data between slow off-chip memory and fast local memories. We also address the problem of mapping computation in regular programs to multi-level parallel architectures using a multi-level tiling approach, and study the impact of on-chip memory availability on the selection of tile sizes at various levels. Experimental results on a GPU demonstrate the effectiveness of the proposed approach. Copyright © 2008 acm.

关键词： Mapping

来源：评论

学校读者我要写书评

暂无评论

Session details: parallel algorithms 08

Session details: Parallel algorithms

引用

Proceedings of the 13th acm sigplan symposium on principles and practice of parallel programming

作者： Greg Bronevetsky Lawrence Livermore National Laboratory

No abstract available.

ISBN: (纸本)9781595937957

No abstract available.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Session details: programming model extensions 08

Session details: Programming model extensions

引用

Proceedings of the 13th acm sigplan symposium on principles and practice of parallel programming

作者： Lauren Smith U.S. Department of Defense

No abstract available.

ISBN: (纸本)9781595937957

No abstract available.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Performance without pain = Productivity data layout and collective communication in UPC

Performance without pain = Productivity data layout and coll...

引用

作者： Nishtala, Rajesh Almási, George Caşcaval, CǍlin Computer Science Division University of California at Berkeley Berkeley CA United States IBM T.J. Watson Research Center Yorktown Heights NY United States

ISBN: (纸本)9781595939609

关键词： parallel programming

来源：评论

学校读者我要写书评

暂无评论

ZOID: I/O-forwarding infrastructure for petascale architectures

ZOID: I/O-forwarding infrastructure for petascale architectu...

引用

作者： Iskra, Kamil Romein, John W. Yoshii, Kazutomo Beckman, Pete Argonne National Laboratory Mathematics and Computer Science Division 9700 South Cass Avenue Argonne IL 60439 United States Oude Hoogeveensedijk 4 7991 PD Dwingeloo Netherlands

ISBN: (纸本)9781595939609

The ZeptoOS project is developing an open-source alternative to the proprietary software stacks available on contemporary massively parallel architectures. The aim is to enable computer science research on these architectures, enhance community collaboration, and foster innovation. In this paper, we introduce a component of ZeptoOS called ZOID-an I/O-forwarding infrastructure for architectures such as IBM Blue Gene that decouple file and socket I/O from the compute nodes, shipping those functions to dedicated I/O nodes. Through the use of optimized network protocols and data paths, as well as a multithreaded daemon running on I/O nodes, ZOID provides greater performance than does the stock infrastructure. We present a set of benchmark results that highlight the improvements. Crucially, the flexibility of our infrastructure is a vast improvement over the stock infrastructure, allowing users to forward data using custom-designed application interfaces, through an easy-to-use plug-in mechanism. This capability is used for realtime telescope data transfers, extensively discussed in the paper. Plug-in-speciflc threads implement prefetching of data obtained over sockets from an input cluster and merge results from individual compute nodes before sending them out, significantly reducing required network bandwidth. This approach allows a ZOID version of the application to handle a larger number of subbands per I/O node, or even to bypass the input cluster altogether, plugging the input from remote receiver stations directly into the I/O nodes. Using the resources more efficiently can result in considerable savings. Copyright © 2008 acm.

关键词： parallel architectures

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共56页 << < 30 31 32 33 34 35 36 37 38 39 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：