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检索条件"任意字段=2003 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming"

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Toward Terabyte Pattern Mining An Architecture-conscious Solution 07

Toward Terabyte Pattern Mining An Architecture-conscious Sol...

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acm sigplan symposium on principles and practice of parallel programming

作者： Buehrer, Gregory Parthasarathy, Srinivasan Tatikonda, Shirish Kurc, Tahsin Saltz, Joel Ohio State Univ Columbus OH 43210 USA

ISBN: (纸本)9781595936028

We present a strategy for mining frequent itemsets from terabyte-scale data sets on cluster systems. The algorithm embraces the holistic notion of architecture-conscious data mining, taking into account the capabilities of the processor, the memory hierarchy and the available network interconnects. Optimizations have been designed for lowering communication costs using compressed data structures and a succinct encoding. Optimizations for improving cache, memory and I/O utilization using pruning and tiling techniques, and smart data placement strategies are also employed. We leverage the extended memory space and computational resources of a distributed message-passing cluster to design a scalable solution, where each node can extend its meta structures beyond main memory by leveraging 64-bit architecture support. Our solution strategy is presented in the context of FPGrowth, a well-studied and rather efficient frequent pattern mining algorithm. Results demonstrate that the proposed strategy result in near-linear scaleup on up to 48 nodes.

关键词： itemset mining data mining parallel out of core

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May-Happen-in-parallel Analysis of X10 Programs 07

May-Happen-in-Parallel Analysis of X10 Programs

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acm sigplan symposium on principles and practice of parallel programming

作者： Agarwal, Shivali Barik, Rajkishore Sarkar, Vivek Shyamasundar, Rudrapatna K. Tata Inst Fundamental Res Bombay 400005 Maharashtra India

ISBN: (纸本)9781595936028

X10 is a modern object-oriented programming language designed for high performance, high productivity programming of parallel and multi-core computer systems. Compared to the lower-level thread-based concurrency model in the Java (TM) language, X10 has higher-level concurrency constructs such as async, atomic and finish built into the language to simplify creation, analysis and optimization of parallel programs. In this paper, we introduce a new algorithm for May-Happen-in-parallel (MHP) analysis of X10 programs. The analysis algorithm is based on simple path traversals in the Program Structure Tree, and does not rely on pointer alias analysis of thread objects as in MHP analysis for Java programs. We introduce a more precise definition of the MHP relation than in past work by adding condition vectors that identify execution instances for which the MHP relation holds, instead of just returning a single true/false value for all pairs of executing instances. Further, MHP analysis is refined in our approach by using the observation that two statement instances which occur in atomic sections that execute at the same X10 place must have MHP = false. We expect that our MHP analysis algorithm will be applicable to any language that adopts the core concepts of places, async, finish, and atomic sections from the X10 programming model. We also believe that this approach offers the best of two worlds to programmers and parallel programming tools - higher-level abstractions of concurrency coupled with simple and efficient analysis algorithms.

关键词： X10 May-Happen-in-parallel Place Concurrent Atomic Activity parallel Program Analysis

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Pervasive parallel Computing - An Historic Opportunity for Innovation in programming and Architecture 07

Pervasive Parallel Computing - An Historic Opportunity for I...

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acm sigplan symposium on principles and practice of parallel programming

作者： Chien, Andrew A. Intel Corp Res Santa Clara CA 95051 USA

ISBN: (纸本)9781595936028

parallel programming has been the subject of deep research for decades - and renowned in the software community as a difficult challenge to the degree that many companies have teams of parallelism and concurrency experts. Further, many ISV's explicitly design their software architectures so as to ensure that the majority of the development effort, including of course debug and test, can be done without consideration of parallelism. What makes parallelism so difficult, are the knotty and coupled problems of correctness, performance - particularly data locality, and software modularity. In Terascale (manycore) chip-level multiprocessors, we are facing a pervasive and critical parallel programming challenge. Core counts on a single chip are expected to increase rapidly, progressing with Moore's law, and quad-core systems are already available today in mainstream volume client and server platforms. To continue the rapid performance scaling to which we have become accustomed, applications will need to exhibit ample parallelism (and increasing amounts of it) for Successive generations of hardware. Further, because the move to Multiple-core parallelism as the primary basis for performance improvement is pervasive, this requirement falls on a wide range of applications including traditional large-scale commercial and HPC server, desktop, laptop, and even those running on small mobile devices. That breadth has numerous implications for the types of solutions that are required. We will discuss some of the requirements for Terascale parallel programming solutions, and point Out several potentially fruitful directions. A number of these solutions will build on mainstream programming approaches (objects, modularity, imperative), particularly introducing parallelism with modest disruption to both large-scale and local-scale program structure. However, there is an opportunity for radically different approaches to take hold in the mainstream (e.g. functional). On the hardware front

关键词： Algorithms Performance Languages

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Dynamic Multigrain parallelization on the Cell Broadband Engine 07

Dynamic Multigrain Parallelization on the Cell Broadband Eng...

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acm sigplan symposium on principles and practice of parallel programming

作者： Blagojevic, Filip Nikolopoulos, Dimitrios S. Stamatakis, Alexandros Antonopoulos, Christos D. Virginia Tech Ctr High End Comp Syst Blacksburg VA 24061 USA

ISBN: (纸本)9781595936028

This paper addresses the problem of orchestrating and scheduling parallelism at multiple levels of granularity on heterogeneous multicore processors. We present mechanisms and policies for adaptive exploitation and scheduling of layered parallelism on the Cell Broadband Engine. Our policies combine event-driven task scheduling with malleable loop-level parallelism, which is exploited from the runtime system whenever task-level parallelism leaves idle cores. We present a scheduler for applications with layered parallelism on Cell and investigate its performance with RAxML, an application which infers large phylogenetic trees, using the Maximum Likelihood (ML) method. Our experiments show that the Cell benefits significantly from dynamic methods that selectively exploit the layers of parallelism in the system, in response to workload fluctuation. Our scheduler outperforms the MPI version of RAxML, scheduled by the Linux kernel, by up to a factor of 2.6. We are able to execute RAxML on one Cell four times faster than on a dual-processor system with Hyperthreaded Xeon processors, and 5-10% faster than on a single-processor system with a dual-core, quad-thread IBM Power5 processor.

关键词： IBM Cell programming Models Process Scheduling RAxML

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Fault detection in multi-threaded c++ server applications 07

Fault detection in multi-threaded c++ server applications

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2007 acm sigplan symposium on principles and practice of parallel programming, PPoPP'07

作者： Müehlenfeld, Arndt Wotawa, Franz Graz University of Technology Inffeldgasse 16b/2 A-8010 Graz Austria

This paper describes experiments with the freely available tool Helgrind, results obtained by using it for debugging a server application comprising 500 kLOC. We present improvements to the run time analysis of C++ pr... 详细信息

ISBN: (纸本)1595936025

关键词： Object oriented programming

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Expressing and Exploiting Concurrency in Networked Applications with Aspen 07

Expressing and Exploiting Concurrency in Networked Applicati...

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acm sigplan symposium on principles and practice of parallel programming

作者： Upadhyaya, Gautam Pai, Vijay S. Midkiff, Samuel P. Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9781595936028

This paper presents Aspen, a high-level programming language that targets both high-productivity programming and runtime support for managing resources needed by a computation. Programs in Aspen are represented as directed graphs, where the edges are well-defined unidirectional communication channels and the nodes are instances of computational modules that process the incoming data. The resulting representation of a program closely resembles a flow chart describing the flow of computation in a server application and exposing the communication at a high level of abstraction. This strategy for program composition naturally allows parallelism and data sharing to be factored out of the core computational logic of a program, facilitating a division of labor between parallelism experts and application experts and also easing code development and maintenance. Aspen automatically and transparently supports task-level parallelism among module instances and data-level parallelism across different flows in an application or, in some cases, across different work items within a flow. Aspen automatically and adaptively allocates threads to modules according to the dynamic workload seen at those modules. Aspen is tested using a web server and a video-on-demand (VoD) server. Both servers are compared to server applications coded in other languages (such as C, C++, and Java). The Aspen programs achieve the same functionality despite using 54-96% fewer lines of user code. Nevertheless, the Aspen version always performs competitively, with performance that is always similar to or better than previous web server implementations and that sees never more than a 10% performance degradation in the VoD server. On the other hand, some workloads see superior performance with Aspen: Aspen's runtime thread allocation strategy allows the video-on-demand server to support up to 36% more simultaneous 1 Mbps video streams than a hand-tuned C++ version.

关键词： parallel programming programming languages network servers resource management

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Transactional programming in a multi-core environment 07

Transactional programming in a multi-core environment

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2007 acm sigplan symposium on principles and practice of parallel programming, PPoPP'07

作者： Adl-Tabatabai, Ali-Reza Kozyrakis, Christos Saha, Bratin Programming Systems Lab. Microprocessor Technology Lab. Intel Corporation Computer Systems Lab. Electrical Engineering Department Stanford University

ISBN: (纸本)1595936025

With single thread performance starting to plateau, HW architects have turned to chip level multiprocessing (CMP) to increase processing power. All major microprocessor companies are aggressively shipping multi-core products in the mainstream computing market. Moore's law will largely be used to increase HW thread-level parallelism through higher core counts in a CMP environment. CMPs bring new challenges into the design of the software system stack. In this tutorial, we talk about the shift to multi-core processors and the programming implications. In particular, we focus on transactional programming. Transactions have emerged as a promising alternative to lock-based synchronization that eliminates many of the problems associated with lock-based synchronization. We discuss the design of both hardware and software transactional memory and quantify the tradeoffs between the different design points. We show how to extend the Java and C languages with transactional constructs, and how to integrate transactions with compiler optimizations and the language runtime (e.g., memory manager and garbage collection).

关键词： Computer programming

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Open Nesting in Software Transactional Memory 07

Open Nesting in Software Transactional Memory

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acm sigplan symposium on principles and practice of parallel programming

作者： Ni, Yang Menon, Vijay Adl-Tabatabai, Ali-Reza Hosking, Antony L. Hudson, Richard L. Moss, J. Eliot B. Saha, Bratin Shpeisman, Tatiana Intel Corp Programming Syst Lab Santa Clara CA 95054 USA

ISBN: (纸本)9781595936028

Transactional memory (TM) promises to simplify concurrent programming while providing scalability competitive to fine-grained locking. Language-based constructs allow programmers to denote atomic regions declaratively and to rely on the underlying system to provide transactional guarantees along with concurrency. In contrast with fine-grained locking, TM allows programmers to write simpler programs that are composable and deadlock-free. TM implementations operate by tracking loads and stores to memory and by detecting concurrent conflicting accesses by different transactions. By automating this process, they greatly reduce the programmer's burden, but they also are forced to be conservative. In certain cases, conflicting memory accesses may not actually violate the higher-level semantics of a program, and a programmer may wish to allow seemingly conflicting transactions to execute concurrently. allow seemingly conflicting transactions to execute concurrently. Open nested transactions enable expert programmers to differentiate between physical conflicts, at the level of memory, and logical conflicts that actually violate application semantics. A TM system with open nesting can permit physical conflicts that are not logical conflicts, and thus increase concurrency among application threads. Here we present an implementation of open nested transactions in a Java-based software transactional memory (STM) system. We describe new language constructs to support open nesting in Java, and we discuss new abstract locking mechanisms that a programmer can use to prevent logical conflicts. We demonstrate how these constructs can be mapped efficiently to existing STM data structures. Finally, we evaluate our system on a set of Java applications and data structures, demonstrating how open nesting can enhance application scalability.

关键词： transactional memory nested transactions open nesting abstract locks

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parallel programming environment: A key to translating tera-scale platforms into a big success 07

Parallel programming environment: A key to translating tera-...

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2007 acm sigplan symposium on principles and practice of parallel programming, PPoPP'07

作者： Fang, Jesse Z. Programming Systems Lab. Intel Corporation

ISBN: (纸本)1595936025

Moore's Law will continue to increase the number of transistors on die for a couple of decades, as silicon technology moves from 65nm today to 45nm, 32 nm and 22nm in the future. Since power and thermal constraints increase with frequency, multi-core or many-core microprocessors will be the way of the future. In the near future, hardware platforms will have sixteen or more cores on die to achieve more than one Tera Instructions Per second (TIPs) computation power. These cores will communicate each other through an on-die interconnect fabric with more than one TB/s on-die bandwidth and less than 30 cycles latency. Off-die D-cache will employ 3D stacked memory technology to tremendously increase off-die cache/memory bandwidth and reduce the latency. Fast copper flex cables will link CPU-DRAM on socket and optical silicon photonics will provide up to one Tb/s I/O bandwidth between boxes. The hardware system with TIPs of compute power operating on terabytes of data make this a ?tera-scale? platform. What are the software implications with the hardware changes from uniprocessor to tera-scale platform with many cores as "the way of the future?" It will be a great challenge for programming environments to help programmers develop concurrent code for most client software. A good concurrent programming environment should extend existing programming languages that typical programmers are familiar with, and bring benefits for concurrent programming. There are many research topics. Examples topics include flexible parallel programming models based on needs from applications, better synchronization mechanisms such as Transactional Memory to replace simple ?Thread + Lock? structure, nested data parallel language primitives with new protocols, fine-grained synchronization mechanisms with hardware support, maybe fine-grained message passing, advanced compiler optimizations for the threaded code, and software tools in the concurrent programming environment. A more interesting proble

关键词： parallel programming

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Adaptive Work Stealing with parallelism Feedback 07

Adaptive Work Stealing with Parallelism Feedback

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acm sigplan symposium on principles and practice of parallel programming

作者： Agrawal, Kunal He, Yuxiong Leiserson, Charles E. MIT Comp Sci & Artificial Intelligence Lab Cambridge MA 02139 USA

ISBN: (纸本)9781595936028

We present an adaptive work-stealing thread scheduler, A-STEAL, for fork-join multithreaded jobs, like those written using the Cilk multithreaded language or the Hood work-stealing library. The A-STEAL algorithm is appropriate for large parallel servers where many jobs share a common multiprocessor resource and in which the number of processors available to a particular job may vary during the job's execution. A-STEAL provides continual parallelism feedback to a job scheduler in the form of processor requests, and the job must adapt its execution to the processors allotted to it. Assuming that the job scheduler never allots any job more processors than requested by the job's thread scheduler, A-STEAL guarantees that the job completes in near-optimal time while utilizing at least a constant fraction of the allotted processors. Our analysis models the job scheduler as the thread scheduler's adversary, challenging the thread scheduler to be robust to the system environment and the job scheduler's administrative policies. We analyze the performance of A-STEAL using "trim analysis," which allows us to prove that our thread scheduler performs poorly on at most a small number of time steps, while exhibiting near-optimal behavior on the vast majority. To be precise, suppose that a job has work T-1 and span (critical-path length) T-infinity. On a machine with P processors, A-STEAL completes the job in expected O(T-1/(P) over tilde + T-infinity + L lg P) time steps. where L is the length of a scheduling quantum and (P) over tilde denotes the O(T-infinity + L lg P)-trimined availability. This quantity is the average of the processor availability over all but the O(T-infinity + L lg P) time steps having the highest processor availability. When the job's parallelism dominates the trimmed availability, that is, (P) over tilde << T-1/T-infinity, the job achieves nearly perfect linear speedup. Conversely, when the trimmed mean dominates the parallelism, the asymptotic running time

关键词： Adaptive scheduling Adversary Critical path Distributed scheduling Job scheduling Multithreaded Languages Multiprocessing Multiprogramming parallelism feedback parallel computation Processor allocation Space sharing Span Thread scheduling Two-level scheduling Trim analysis Work Work stealing

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