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2003 acm sigplan symposium on principles and practice of parallel programming

作者： Frens, Jeremy D. Wise, David S. Calvin College Grand Rapids MI 49546-4388 United States Indiana University Bloomington IN 47405-7104 United States

ISBN: (纸本)9781581135886

Quadtree matrices using Morton-order storage provide natural blocking on every level of a memory hierarchy. Writing the natural recursive algorithms to take advantage of this blocking results in code that honors the memory hierarchy without the need for transforming the code. Furthermore, the divide-and-conquer algorithm breaks problems down into independent computations. These independent computations can be dispatched in parallel for straightforward parallel processing. Proof-of-concept is given by an algorithm for QR factorization based on Givens rotations for quadtree matrices in Morton-order storage. The algorithms deliver positive results, competing with and even beating the LAPACK equivalent.

关键词： parallel processing systems

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Using thread-level speculation to simplify manual parallelization 03

Using thread-level speculation to simplify manual paralleliz...

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2003 acm sigplan symposium on principles and practice of parallel programming

作者： Prabhu, Manohar K. Olukotun, Kunle Stanford University Computer Systems Laboratory Stanford CA 94305 United States

ISBN: (纸本)9781581135886

In this paper, we provide examples of how thread-level speculation (TLS) simplifies manual parallelization and enhances its performance. A number of techniques for manual parallelization using TLS are presented and results are provided that indicate the performance contribution of each technique on seven SPEC CPU2000 benchmark applications. We also provide indications of the programming effort required to parallelize each benchmark. TLS parallelization yielded a 110% speedup on our four floating point applications and a 70% speedup on our three integer applications, while requiring only approximately 80 programmer hours and 150 lines of non-template code per application. These results support the idea that manual parallelization using TLS is an efficient way to extract fine-grain thread-level parallelism.

关键词： parallel processing systems

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The design and implementation of a parallel array operator for the arbitrary remapping of data 03

The design and implementation of a parallel array operator f...

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2003 acm sigplan symposium on principles and practice of parallel programming

作者： Deitz, Steven J. Chamberlain, Bradford L. Choi, Sung-Eun Snyder, Lawrence University of Washington Seattle WA 98195 United States Cray Inc. Seattle WA 98104 United States Los Alamos National Laboratory Los Alamos NM 87545 United States

ISBN: (纸本)9781581135886

Gather and scatter are data redistribution functions of long-standing importance to high performance computing. In this paper, we present a highly-general array operator with powerful gather and scatter capabilities unmatched by other array languages. We discuss an efficient parallel implementation, introducing three new optimizations - schedule compression, dead array reuse, and direct communication - that reduce the costs associated with the operator's wide applicability. In our implementation of this operator in ZPL, we demonstrate performance comparable to the hand-coded Fortran + MPI versions of the NAS FT and CG benchmarks.

关键词： parallel processing systems

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Exploiting task-level concurrency in a programmable network interface

Exploiting task-level concurrency in a programmable network ...

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2003 acm sigplan symposium on principles and practice of parallel programming

作者： Kim, Hyong-Youb Pai, Vijay S. Rixner, Scott Rice University Houston TX United States

Programmable network interfaces provide the potential to extend the functionality of network services but lead to instruction processing overheads when compared to application-specific network interfaces. This paper aims to offset those performance disadvantages by exploiting task-level concurrency in the workload to parallelize the network interface firmware for a programmable controller with two processors. By carefully partitioning the handler procedures that process various events related to the progress of a packet, the system can minimize sharing, achieve load balance, and efficiently utilize on-chip storage. Compared to the uniprocessor firmware released by the manufacturer, the parallelized network interface firmware increases throughput by 65% for bidirectional UDP traffic of maximum-sized packets, 157% for bidirectional UDP traffic of minimum-sized packets, and 32-107% for real network services. This parallelization results in performance within 10-20% of a modern ASIC-based network interface for real network services.

关键词： parallel processing systems

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Toward efficient and robust software speculative parallelization on multiprocessors 03

Toward efficient and robust software speculative paralleliza...

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2003 acm sigplan symposium on principles and practice of parallel programming

作者： Cintra, Marcelo Llanos, Diego R. School of Informatics University of Edinburgh Edinburgh United Kingdom Departamento de Informática Universidad de Valladolid Valladolid Spain

ISBN: (纸本)9781581135886

With speculative parallelization, code sections that cannot be fully analyzed by the compiler are aggressively executed in parallel. Hardware schemes are fast but expensive and require modifications to the processors and memory system. Software schemes require no extra hardware but can be inefficient. This paper proposes a new software-only speculative parallelization scheme. The scheme is developed after a systematic evaluation of the design options available and is shown to be efficient and robust and to outperform previously proposed schemes. The novelty and performance advantage of the scheme stem from the use of carefully tuned data structures, synchronization policies, and scheduling mechanisms. Experimental results show that our scheme has small overheads and, for applications with few or no data dependence violations, realizes on average 71% of the speedup of a manually parallelized version of the code, outperforming two recently proposed software-only speculative parallelization schemes. For applications with many data dependence violations, our performance monitors and switches can effectively curb the performance degradation.

关键词： parallel processing systems

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Phoenix: A parallel programming model for accommodating dynamically joining/leaving resources 03

Phoenix: A parallel programming model for accommodating dyna...

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2003 acm sigplan symposium on principles and practice of parallel programming

作者： Taura, Kenjiro Endo, Toshio Kaneda, Kenji Yonezawa, Akinori University of Tokyo 7-3-1 Hongo Bunkyo-ku Tokyo 113-0033 Japan PRESTO JST 4-1-8 Honcho Kawaguchi Saitama 332-0012 Japan

ISBN: (纸本)9781581135886

This paper proposes Phoenix, a programming model for writing parallel and distributed applications that accommodate dynamically joining/leaving compute resources. In the proposed model, nodes involved in an application see a large and fixed virtual node name space. They communicate via messages, whose destinations are specified by virtual node names, rather than names bound to a physical resource. We describe Phoenix API and show how it allows a transparent migration of application states, as well as dynamically joining/leaving nodes as its by-product. We also demonstrate through several application studies that Phoenix model is close enough to regular message passing, thus it is a general programming model that facilitates porting many parallel applications/algorithms to more dynamic environments. Experimental results indicate applications that have a small task migration cost can quickly take advantage of dynamically joining resources using Phoenix. Divide-and-conquer algorithms written in Phoenix achieved a good speedup with a large number of nodes across multiple LANs (120 times speedup using 169 CPUs across three LANs). We believe Phoenix provides a useful programming abstraction and platform for emerging parallel applications that must be deployed across multiple LANs and/or shared clusters having dynamically varying resource conditions.

关键词： Computer programming

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Impala: a middleware system for managing autonomic, parallel sensor systems 03

Impala: a middleware system for managing autonomic, parallel...

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9th acm sigplan symposium on principles and practice of parallel programming

作者： Liu, T Martonosi, M Princeton Univ Dept Comp Sci Princeton NJ 08544 USA Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)9781581135886

Sensor networks are long-running computer systems with many sensing/compute nodes working to gather information about their environment, process and fuse that information, and in some cases, actuate control mechanisms in response. Like traditional parallel systems, communication between nodes is of fundamental importance, but is typically accomplished via wireless transceivers. One further key attribute of sensor networks is that they are almost always long-running systems, intended to operate in situ, with minimal direct human intervention, for months or years. This requirement for long-running autonomy mandates careful design of the runtime system that manages applications on each node, to ensure reliability and ease of upgrades over the life of the system. This paper describes Impala, a middleware architecture that enables application modularity, adaptivity, and repair-ability in wireless sensor networks. Impala allows software updates to be received via the node's wireless transceiver and to be applied to the running system dynamically. In addition, Impala also provides an interface for on-the-fly application adaptation in order to improve the performance, energy-efficiency, and reliability of the software system. Impala has been designed to be a part of the ZebraNet mobile sensor network, but we are also prototyping it within HP/Compaq iPAQ Pocket PC handhelds. We present performance data for both real system measurements of the Pocket PC version as well as simulations of a full mobile sensor system deployment. Overall, Impala is a lightweight runtime system that can greatly improve system reliability, performance, and energy-efficiency. The ideas introduced here for sensor networks have applicability more broadly in other long-running autonomous parallel systems as well.

关键词： design experimentation performance sensor networks middleware system software adaptation software update

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parallel 'go with the winners' algorithms in distributed memory models

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JOURNAL OF parallel AND DISTRIBUTED COMPUTING 2003年第9期63卷 801-814页

作者： Peinado, M Lengauer, T Microsoft Corp Redmond WA 98052 USA Max Planck Inst Comp Sci D-66123 Saarbrucken Germany

We parallelize the 'go with the winners' algorithm of Aldous and Vazirani (in: Proceedings of the 35th IEEE symposium on the Foundations of Computer Science, IEEE Computer Society Press, Silver Spring., MD, 1994, pp. 492-501) and analyze the resulting parallel algorithm in the LogP-model (in: Proceedings of the Fourth acm sigplan symposium on principles & practice of parallel programming, 1993, pp. 1-12). The main issues in the analysis are load imbalances and communication delays. The result of the analysis is a practical algorithm which, under reasonable assumptions, achieves linear speedup. Finally, we analyze our algorithm for a concrete application: generating models of amorphous chemical structures. (C) 2003 Elsevier Inc. All rights reserved.

关键词： parallel algorithms go with the winners LogP model second moment method load balancing amorphous solids self-avoiding walks

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programming the FlexRAM parallel intelligent memory system 03

Programming the FlexRAM parallel intelligent memory system

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2003 acm sigplan symposium on principles and practice of parallel programming

作者： Fraguela, Basilio B. Renau, Jose Feautrier, Paul Padua, David Torrellas, Josep Dept. de Electronics Universidade da Coruña La Coruna Spain Dept. of Computer Science Univ. Illinois at Urbana-Champaign Urbana IL United States LIP Ecl. Normale Sup. de Lyon Lyon France

ISBN: (纸本)9781581135886

In an intelligent memory architecture, the main memory of a computer is enhanced with many simple processors. The result is a highly-parallel, heterogeneous machine that is able to exploit computation in the main memory. While several instantiations of this architecture have been proposed, the question of how to effectively program them with little effort has remained a major challenge. In this paper, we show how to effectively hand-program an intelligent memory architecture at a high level and with very modest effort. We use FlexRAM as a prototype architecture. To program it, we propose a family of high-level compiler directives inspired by OpenMP called CFlex. Such directives enable the processors in memory to execute the program in cooperation with the main processor. In addition, we propose libraries of highly-optimized functions called Intelligent Memory Operations (IMOs). These functions program the processors in memory through CFlex, but make them completely transparent to the programmer. Simulation results show that, with CFlex and IMOs, a server with 64 simple processors in memory runs on average 10 times faster than a conventional server. Moreover, a set of conventional programs with 240 lines on average are transformed into CFlex parallel form with only 7 CFlex directives and 2 additional statements on average.

关键词： parallel processing systems

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Compiler support for speculative multithreading architecture with probabilistic points-to analysis

Compiler support for speculative multithreading architecture...

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2003 acm sigplan symposium on principles and practice of parallel programming

作者： Chen, Peng-Sheng Hung, Ming-Yu Hwang, Yuan-Shin Ju, Roy Dz-Ching Lee, Jenq Kuen Department of Computer Science National Tsing Hua University Hsinchu 300 Taiwan Department of Computer Science National Taiwan Ocean University Keelung 202 Taiwan Microprocessor Research Lab. Intel Corporation Santa Clara CA 95052 United States

Speculative multithreading (SpMT) architecture can exploit thread-level parallelism that cannot be identified statically. Speedup can be obtained by speculatively executing threads in parallel that are extracted from a sequential program. However, performance degradation might happen if the thread: are highly dependent, since a recovery mechanism will be activated when a speculative thread executes incorrectly and such a recovery action usually incurs a very high penalty. Therefore, it is essential for SpMT to quantify the degree of dependences and to turn off speculation if the degree of dependences passes certain thresholds. This paper presents a technique that quantitatively computes dependences between loop iterations and such information can be used to determine if loop iterations can be executed in parallel by speculative threads. This technique can be broken into two steps. First probabilistic points-to analysis is performed to estimate the probabilities of points-to relationships in case there are pointer references in programs, and then the degree of dependences between loop iterations is computed quantitatively. Preliminary experimental results show compiler-directed thread-level speculation based on the information gathered by this technique can achieve significant performance improvement on SpMT.

关键词： parallel processing systems

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