The purpose of this work is to show the importance of an adequate generation of the excitation signal for the performance of bandwidth extension algorithms for speech signals. Two previously proposed methods of obtain...
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ISBN:
(纸本)0780393333
The purpose of this work is to show the importance of an adequate generation of the excitation signal for the performance of bandwidth extension algorithms for speech signals. Two previously proposed methods of obtaining the excitation signal are analyzed and, based on this analysis, a new method is proposed. The influence of each method in the quality of the reconstructed wideband speech signal is evaluated by quantitative parameters of speech quality.
This paper details the design of a new high-speed pipelined elliptic curve cryptography (ECC) application specific instruction set processor (ASIP) using field programmable gate array (FPGA) technology. A six-stage pi...
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ISBN:
(纸本)9781424403820
This paper details the design of a new high-speed pipelined elliptic curve cryptography (ECC) application specific instruction set processor (ASIP) using field programmable gate array (FPGA) technology. A six-stage pipeline has been applied to the design, and pipeline stalls are avoided via instruction reordering and data forwarding. Three complex instructions are introduced to reduce the latency by reducing the overall number of instructions. The new processor shows improvements over previously reported designs in terms of throughput, latency and area. The higher clock frequencies and low latencies lead to the fastest point multiplication time reported in the literature. An FPGA implementation over GF(2(163)) is shown, which achieves a point multiplication time of 36.77 microseconds at 77.01 MHz on a Xilinx Virtex-E device- over 50% faster than the best figure previously reported.
In this paper receiver synthesis for nonlinearly amplified orthogonal frequency division multiplexing (OFDM) signal is presented. Optimal maximum-likelihood (ML) receiver is proposed and its computational complexity i...
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ISBN:
(纸本)0780377958
In this paper receiver synthesis for nonlinearly amplified orthogonal frequency division multiplexing (OFDM) signal is presented. Optimal maximum-likelihood (ML) receiver is proposed and its computational complexity is discussed. Further, sub-optimal receiver suitable for OFDM signals with large number of sub-carriers and high-order constellation is presented. The performance of optimal and sub-optimal receiver for nonlinearly amplified m-QAM-OFDM signal is studied by means of simulation.
We studied the efficient implementation of a motion estimation algorithm for H.264/AVC on TMS 320C64x, a VLIW (Very Long Instruction Word) SIMD (Single Instruction Multiple Data) digital signal processor. H.264 motion...
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ISBN:
(纸本)0780393333
We studied the efficient implementation of a motion estimation algorithm for H.264/AVC on TMS 320C64x, a VLIW (Very Long Instruction Word) SIMD (Single Instruction Multiple Data) digital signal processor. H.264 motion estimation algorithms demand much arithmetic operations especially because of the variable block size optimization. The SAD (Sum of Absolute Difference) reuse method is chosen not only to reduce the computation but also to utilize the regular algorithmic structure, which is essential for efficient implementation in parallel and pipelined processors. We applied a few techniques, such as loop length increase for efficient software pipelining, multiblock SAD computation for reducing memory access overhead, block processing for cache miss minimization, and improved quarter-pixel processing. The implementation results show that a real-time implementation of Me for D1 size (720*480) video is possible using a 720MHz TMS320C6416 digital signal processor.
Reed-Solomon (RS) codes play an important role in providing error protection and data integrity. Many researches of RS decoder are implemented in parallel architecture, which can perform the highest data throughput ra...
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The Fast Fourier Transform (FFT) is at the heart of many signalprocessingsystems, e.g. those using orthogonal frequency-division multiplexing (OFDM) modulation. For such systems the FFT is typically implemented on d...
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ISBN:
(纸本)9781538663189
The Fast Fourier Transform (FFT) is at the heart of many signalprocessingsystems, e.g. those using orthogonal frequency-division multiplexing (OFDM) modulation. For such systems the FFT is typically implemented on dedicated hardware, e.g. field-programmable gate arrays (FPGAs), to meet the high throughput and latency requirements. This paper describes a 2 parallel radix-2 FFT core embedded into an overall processing architecture that allows data interfaces to be tailored to application specific needs. The proposed solution can dynamically switch between different FFT sizes while maintaining its maximum theoretical throughput. Our experiments show that a two-fold increase in throughput can be achieved without doubling resource usage, when taking into account FPGA-specific features for several optimizations.
In this paper, we present a new software tool, called HTGS Model-based Engine (HMBE), for the design and implementation of multicore signalprocessing applications. HMBE provides complementary capabilities to HTGS (Hy...
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ISBN:
(纸本)9781538604465
In this paper, we present a new software tool, called HTGS Model-based Engine (HMBE), for the design and implementation of multicore signalprocessing applications. HMBE provides complementary capabilities to HTGS (Hybrid Task Graph Scheduler), which is a recently-introduced software tool for implementing scalable workflows for high performance computing applications. HMBE integrates advanced design optimization techniques provided in HTGS with model-based approaches that are founded on dataflow principles. Such integration contributes to (a) making the application of HTGS more systematic and less time consuming, (b) incorporating additional dataflow-based optimization capabilities with HTGS optimizations, and (c) automating significant parts of the HTGS-based design process. In this paper, we present HMBE with an emphasis on novel dynamic scheduling techniques that are developed as part of the tool. We demonstrate the utility of HMBE through a case study involving an image stitching application for large scale microscopy images.
Presented in this paper is a low-complexity iris identification architecture built upon an enhanced periodicity transform, referred to as the prime subspace periodicity transform (PSPT). The proposed PSPT achieves eff...
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ISBN:
(纸本)0780393333
Presented in this paper is a low-complexity iris identification architecture built upon an enhanced periodicity transform, referred to as the prime subspace periodicity transform (PSPT). The proposed PSPT achieves efficient computation by partitioning periodic subspaces into hierarchical prime subspaces. Data decomposition at prime subspaces can be implemented in a simple manner by exploiting the redundancy in correlation computation. The proposed PSPT establishes a theoretical foundation for our work in developing integrated biometric systems for identity authentication. A PSPT-based iris identification architecture is developed that achieves 32.1%-56.2% reduction in computational complexity. Experimental results demonstrate an efficient solution for reliable and accurate iris identification. The proposed PSPT algorithm in combination with architecture optimizations address the challenges in single-chip implementation of biometric systems.
We present two case studies of different architectures for H.264 video decoder. The objective of this case study is to show the design methodology that can maximize the flexibility of video decoder. First, H.264 is de...
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ISBN:
(纸本)9781424403820
We present two case studies of different architectures for H.264 video decoder. The objective of this case study is to show the design methodology that can maximize the flexibility of video decoder. First, H.264 is designed based on configurable processor. The configurable processor was used to complement the existing functional units with instruction extensions for the H.264 hardware kernel. Secondly, we profile the H.264 application to capture the amount of data traffic among modules. We will use this information to guide the placement of H.264 hardware modules in the dataflow architecture. A simulated annealing based placement algorithm produces the final placement aiming to optimize the communication costs between the modules in a dataflow architecture. With both our design methodologies, emerging embedded applications requiring several GOPS to meet real-time constraints can be drafted within a reasonable amount of design time with maximum design flexibility
In this paper, a reduced-complexity, scalable implementation of LDPC decoder is presented. The decoder architecture in this paper is an improved version of [1, 2]. The new architecture makes the implementation of mult...
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ISBN:
(纸本)9781424403820
In this paper, a reduced-complexity, scalable implementation of LDPC decoder is presented. The decoder architecture in this paper is an improved version of [1, 2]. The new architecture makes the implementation of multiple code rates, multiple block sizes and multiple standards LDPC decoder very straightforward. As an example, we implemented a parameterized decoder that supports the LDPC code in ieee 802.16e standard, which requires code rates of 1/2, 2/3 and 3/4, with block sizes varying from 576 to 2304. The decoder is synthesized with Texas Instruments' 90 nm ASIC process technology, with a target operation frequency of 100 MHz, 15 decoding iterations, the maximum data rate is up to 256 Mbps.
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