This paper presents a design method for fixed-width squarer that receives a W-bit input and produces a W-bit squared product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier...
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ISBN:
(纸本)0780377958
This paper presents a design method for fixed-width squarer that receives a W-bit input and produces a W-bit squared product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulation, it is shown that the performance of the proposed method is pretty close to that of the rounding operation and much better than that of the truncation operation.
Terrestrial Digital Video Broadcasting (DVB-T) is currently being introduced in many European countries and planned to supplement or replace current analogue broadcasting schemes in a large part of the world. It is al...
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In order to give an answer to a question of the arithmetic representation in future DSP architectures for mobile communication applications, the signalprocessing quality of different arithmetic representations has be...
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In order to give an answer to a question of the arithmetic representation in future DSP architectures for mobile communication applications, the signalprocessing quality of different arithmetic representations has been studied. Based on the result, an implementation of a novel block-floating multiple datapath DSP has been developed. This implementation allows a superior signalprocessing performance compared to that of short-word floating-point or conventional block-floating-point.
In this paper we define the requirements for a specification environment suited to describe complex user-end telecommunication systems and useful as a backbone for automation of the implementation path towards integra...
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In this paper we define the requirements for a specification environment suited to describe complex user-end telecommunication systems and useful as a backbone for automation of the implementation path towards integration of such systems on silicon. The definition of these requirements has been driven by the design and implementation of a mobile terminal for spread spectrum satellite communications which is considered, in the context of our work, to be representative for the definition of a system.
In this paper we discuss the design and implementation of a FPGA Power DAC for digital audio applications. The paper concentrates on the sigma-delta modulator, which is used to convert an oversampled PCM input signal ...
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ISBN:
(纸本)0780338065
In this paper we discuss the design and implementation of a FPGA Power DAC for digital audio applications. The paper concentrates on the sigma-delta modulator, which is used to convert an oversampled PCM input signal into a 1-bit code suitable for controlling a power switch. The design of the bit-flipping architecture used to reduce the pulse-repetition frequency of the output is discussed, together with the the loop filter structure and transfer function design. This is followed by details of FPGA architecture and the optimisations required for implementation.
Dataflow languages provide a high-level description that can expose inherent parallelism in many applications. This high level description can be applied to automatically create efficient code and schedules based on p...
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Orthogonal Frequency Division Multiple Access (OFDMA) basestations allow multiple users to transmit simultaneously on different subcarriers during the same symbol period. This paper considers basestation allocation of...
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An efficient design and VLSI implementation of a high data rate Medical Implant Communications Service (MICS) digital baseband transmitter for implantable medical devices is proposed in this paper. An orthogonal frequ...
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ISBN:
(纸本)9781457719219
An efficient design and VLSI implementation of a high data rate Medical Implant Communications Service (MICS) digital baseband transmitter for implantable medical devices is proposed in this paper. An orthogonal frequency division multiplexing (OFDM)-based multicarrier scheme is used to overcome the data rate limitation caused by the narrow bandwidth of 300 kHz. The proposed transmitter can support enhanced data rate by utilizing multiple channels simultaneously. Furthermore, to satisfy the MICS regulation, various schemes are applied including optimized subcarrier allocation for inverse fast Fourier transform (IFFT) and additional sidelobe suppression technique. The proposed transmitter with optimized hardware architecture is verified by VLSI implementation and it can support a maximum data rate of 4.86 Mbps, which is more than ten times faster than the previous systems.
Recursive filters are used frequently in digital signalprocessing. They can be implemented in dedicated hardware or in software on a digital signal processor (DSP). Software solutions often are preferable for their s...
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ISBN:
(纸本)0780377958
Recursive filters are used frequently in digital signalprocessing. They can be implemented in dedicated hardware or in software on a digital signal processor (DSP). Software solutions often are preferable for their speed of implementation and flexibility. However, contemporary DSPs are mostly not fast enough to perform filtering for high data-rates or large filters. A method to increase the computational power of a DSP without sacrificing efficiency is to use multiple processor elements controled by the single-instruction multiple-data (SIMD) paradigm. The parallelization of recursive algorithms is difficult, because of the data dependencies. We are using design methods for parallel procesor arrays to realize implementations that can be used on a parallel DSP. Further, we are focusing on the partitioning of the algorithm so that the realization can be used for different architectures. Consequences for the architecture are considered, too.
We present a hardware implementation of Burg's method, which is used for autoregressive (AR) model estimation. The AR model is a linear predictive modeling technique. It assumes that the current value of a signal ...
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ISBN:
(纸本)9781538663189
We present a hardware implementation of Burg's method, which is used for autoregressive (AR) model estimation. The AR model is a linear predictive modeling technique. It assumes that the current value of a signal can be described by a finite linear aggregate of the previous values. The AR model can be used for spectral analysis as an alternative to the Fourier transform. This approach is a parametric method, and it can yield higher resolutions than nonparametric methods in cases when the signal length is short. Although Burg's method requires a large computational capacity, especially with higher model orders, a fast Burg's method has been proposed for improving this draw back. In this study, we evaluate the influence of the order and the data length of Burg's method on the computational capacity. The hardware implementation method of the fast Burg's method including a two-stage pipeline architecture and a parallelization technique for autocorrelation calculations is proposed. The proposed method is implemented using Verilog HDL and its energy consumption is estimated with the 65-nm CMOS process. The evaluation result shows that the proposed method achieves an energy consumption of 21.6-361.4 nJ for the spectral estimation with a data length of 128-2048 points when the model order is 5.
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