This paper presents a new algorithm for 2D nonseparable lifted bi-orthogonal wavelet transform. The algorithm is derived by factoring complementary pairs of filter of wavelet transform written as (LxM) tap 2D filter. ...
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ISBN:
(纸本)0780377958
This paper presents a new algorithm for 2D nonseparable lifted bi-orthogonal wavelet transform. The algorithm is derived by factoring complementary pairs of filter of wavelet transform written as (LxM) tap 2D filter. The results are efficient architectures for real time signalprocessing, which don't require transpose memory for 2D processing of data. The proposed architecture exploits in place implementation inherit from the algorithm and can take advantage of both vertical and horizontal parallelism in the direct implementation. The processing in architecture is scheduled carefully by pipelining the lifted steps, which allows two or four times faster processing than the direct implementation. The architecture therefore allows lowering the clock frequency by two/four. The proposed architecture operates at high speed/consumes low power and has reduced computational complexity as compared to already published filter and lifted based bi-orthogonal wavelet architectures.
Static timing analysis sets the industry standard in the design methodology to gage the speed of high performance microprocessors. Unfortunately, not all the paths identified using such analysis can be sensitized. Thi...
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ISBN:
(纸本)0780364880
Static timing analysis sets the industry standard in the design methodology to gage the speed of high performance microprocessors. Unfortunately, not all the paths identified using such analysis can be sensitized. This leads to a pessimistic estimation of processor speed, and the engineering efforts spent optimizing such paths can not improve the performance of the chip. In the past, we demonstrated initial results of how ATPG technique can be used to eliminate false paths efficiently[1]. Due to the gap between the physical design on which the static timing analysis of the chip is based and the test view on which ATPG technique is applied to eliminate false paths, in many cases only sections of some of the paths in the full-chip were analyzed in our initial results. In this paper, we will fully analyze all the timing paths using the ATPG technique overcoming the gap between the testing and timing analysis techniques. We applied our method on the second G4(1) PowerPC(TM).
In this paper, robust timing & frequency synchronization techniques for OFDMA (OFDM-FDMA) systems is presented. Under the multi-path channel environment of ITU-R M.1225, Detection Probability, False Alarm, Missing...
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ISBN:
(纸本)0780393333
In this paper, robust timing & frequency synchronization techniques for OFDMA (OFDM-FDMA) systems is presented. Under the multi-path channel environment of ITU-R M.1225, Detection Probability, False Alarm, Missing Probabifity, and Mean Acquisition Time of the proposed timing synchronization scheme are compared with the existing method of 141 to demonstrate the excellence of the proposed scheme. MSE (Mean Square Error) and signal constellation to show the performance of carrier frequency offset estimation is also addressed in this paper.
Today's programmable chips are segregated into five classes and comparison among these classes are given. Due to hardware comparison, Domain Specific Programmable chips have great advantage on realizing complex mu...
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ISBN:
(纸本)0780338065
Today's programmable chips are segregated into five classes and comparison among these classes are given. Due to hardware comparison, Domain Specific Programmable chips have great advantage on realizing complex multimedia functions over general purpose processors. Future applications for such DSP chips are also described through our experience on Silicon Terminal Series.
Alternative structures of merged arithmetic are examined for implementing the inner product function. Merged arithmetic dissolves the boundaries between multiplication and addition by synthesizing the entire function ...
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Alternative structures of merged arithmetic are examined for implementing the inner product function. Merged arithmetic dissolves the boundaries between multiplication and addition by synthesizing the entire function directly rather than decomposing the function into discrete multiplies and adds. Fully merged arithmetic eliminates these boundaries completely. A partially merged arithmetic is introduced which retains most of the savings of fully merged arithmetic, while increasing regularity and testability by keeping some of the discrete component structure intact.
Low power consumption is imperative to enable the deployment of broadband wireless connectivity in portable devices such as PDA's or smart phones. Next to low power circuit and architecture design, system-level po...
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In this paper, we introduce a polyphase implementation and design of an oversampled K-channel generalized DFT (GDFT) filter bank, which can be employed for subband adaptive filtering, and therefore is required to have...
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ISBN:
(纸本)0780349970
In this paper, we introduce a polyphase implementation and design of an oversampled K-channel generalized DFT (GDFT) filter bank, which can be employed for subband adaptive filtering, and therefore is required to have a low aliasing level in the subband signals. A polyphase structure is derived which can be factorized into a real valued polyphase network and a GDFT modulation. For the latter, an FFT realization may be used, yielding a very inexpensive polyphase implementation for arbitrary integer decimation ratios N less than or equal to K. We also present an analysis underlining the efficiency of complex valued subband processing. The design of the filter bank is completely based on the prototype filter and solved using a fast converging iterative least squares method, for which we give examples. The design specifications closely correspond with performance limits of subband adaptive filtering, which are under-pinned by simulation results.
The proceedings contain 80 papers from the conference on Machine Learning for signalprocessing XIV - proceedings of the 2004ieeesignalprocessing Society workshop. The topics discussed include: a criteria for model...
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ISBN:
(纸本)0780386086
The proceedings contain 80 papers from the conference on Machine Learning for signalprocessing XIV - proceedings of the 2004ieeesignalprocessing Society workshop. The topics discussed include: a criteria for model-robust design of experiments;learning-based visual localization using formal concept lattices;modeling and control of unknown chaotic systems via multiple models;recursive principal component analysis using eigenvector matrix perturbation;towards a unification of information theoretic learning and kernel methods;adaptive learning for the neural classifier based on Fisher criterion;and computational intelligence applied to signalprocessing: a proposal for fuzzy neural identification.
In this paper, a software-based implementation for the Multiple Input and Multiple Output (MIMO) receiver baseband processing conforming to the ieee 802.11ac standard on a DSP core with vector extensions is presented....
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In this paper, a novel 2-D IDCT architecture based on the energy compaction property of 2-D DCT is proposed. This architecture performs 2-D IDCT directly on the 2-D DCT data set, avoiding the need for the transpositio...
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In this paper, a novel 2-D IDCT architecture based on the energy compaction property of 2-D DCT is proposed. This architecture performs 2-D IDCT directly on the 2-D DCT data set, avoiding the need for the transposition memory. We derive a recursion equation from the definition of the 2-D IDCT algorithm and use it to implement a wavefront array processor. The wavefront array processor consists of highly regular, parallel and pipelined processing elements which are suitable for VLSI implementation. This implementation also utilizes the sparseness property of the 2-D DCT coefficients to reduce the computational complexity. It is shown that the proposed architecture achieves a high throughput rate, (15 + m) clock cycles per 2-D DCT data set, where in is the number of the non-zero DCT coefficients. Another important aspect of this architecture is that it provides an efficient way to control the trade-off between visual quality of the reconstructed image and computational complexity.
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