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检索条件"任意字段=2004 IEEE Workshop on Signal Processing Systems Design and Implementation, Proceedings"

共 1866 条记录，以下是21-30 订阅

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2000 ieee workshop on signal processing systems. SiPS 2000. design and implementation (Cat. No.00TH8528)

2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. ...

引用

ieee workshop on signal processing systems (SIPS)

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2005 ieee workshop on signal processing systems-design and implementation (ieee Cat. No.05TH8830C)

2005 IEEE Workshop on Signal Processing Systems-Design and I...

引用

ieee workshop on signal processing systems (SIPS)

The following topics were dealt with: software defined radio; adders; end-to-end modular exponentiation; media processing; FPGA; FIR filters; cryptography; microcontroller; secure hash algorithm; video watermarking; iterative LDPC code decoders; signal processing systems; CMOS image sensor; multiprocessor based packet-switch; optical flow sensor; text information retrieval systems; WCDMA; image processing; power-aware design; video architecture; video signal processing; reconfigurable architectures; DSP architecture; video coding; mobile wireless systems; wireless LAN; sensor networks; ad hoc networks; and error correction.

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design of a lattice decoder for MIMO systems in FPGA

Design of a lattice decoder for MIMO systems in FPGA

引用

ieee workshop on signal processing systems design and implementation

作者： Ma, J Huang, XM Univ New Orleans Dept Elect Engn New Orleans LA 70148 USA

ISBN: (纸本)0780385047

Hardware implementation of lattice decoding algorithms becomes a challenging task as the complexity of the MIMO systems increases. This paper presents the design and implementation of a Schnorr-Euchner strategy based lattice decoder using FPGA. This lattice decoding algorithm has high data dependency during the iterative closest lattice point search procedures. The parallelism of the algorithm is explored and efficient hardware architectures are developed with the decoding function on FPGA and the data preprocessing on DSP. The system prototype of the decoder shows that it supports 2.7Mbits/s data rate on a Virtex2-1000 FPGA, and is about 4 times faster than a DSP-based lattice decoder. The bit error rate (BER) performance is also tested and verified with software simulation.

关键词： lattice decoder closest point search MIMO FPGA

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Run-time reconfigurable adaptive signal processing system with asynchronous dynamic pipelining: A case study of DLMS ADFE

Run-time reconfigurable adaptive signal processing system wi...

引用

ieee workshop on signal processing systems design and implementation

作者： Chen, SZ Zhang, T Rensselaer Polytech Inst Dept Elect Comp & Syst Engn Troy NY USA

ISBN: (纸本)0780385047

Most pipelined adaptive signal processing systems are inherently subject to a trade-off between throughput and signal processing performance because of the adaptation feedback loops. To mitigate this dilemma, we propose to apply asynchronous pipeline to implement pipelined adaptive signal processing systems that can support run-time reconfigurable throughput/performance trade-offs. This can be leveraged to improve the overall system performance in many applications. In this work, we demonstrate this design approach using a delayed LMS (DLMS) adaptive decision feedback equalizer (ADFE) for the communication links with variable data rate. By adjusting the pipelining depth on-the-fly, the DLMS ADFE can dynamically track the best equalization performance allowed by different data rate. We develop the design scheme that applies a zero-delay-overhead asynchronous pipeline style to implement ADFE and support dynamic pipelining depth control. Simulation result shows a significant performance improvement compared with its synchronous counterpart.

关键词： Adaptive systems

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implementation of the decorrelating transformation for low power fir filters

Implementation of the decorrelating transformation for low p...

引用

ieee workshop on signal processing systems design and implementation

作者： Erdogan, AT Arslan, T Lai, R Univ Edinburgh Sch Engn & Elect Edinburgh EH9 3JL Midlothian Scotland

ISBN: (纸本)0780385047

This paper presents the implementation of the decorrelating (DECOR) transformation technique for low power FIR filtering cores. The technique was introduced in the past, but was not fully evaluated for its area, delay and power performance. Early evaluations did not consider the whole implementation and were merely based on either some analytical methods or high level simulation models. This paper presents the complete VLSI implementation of the technique and a study of its area, delay and power performance with different order of coefficient differences and various multiplier types. We show that although the technique achieves up to 47% power saving in the multiplier unit, the overall power saving is up to 25% with up to 24% increase in area.

关键词： power consumption VLSI FIR filters decorrelation low-power electronics digital signal processing chips decorrelating transformation low power FIR filters VLSI implementation area performance delay performance power performance coefficient differences multiplier types power saving

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Packet transmission policies for battery operated communication systems

Packet transmission policies for battery operated communicat...

引用

ieee workshop on signal processing systems design and implementation

作者： Li, Y Chakrabarti, C Arizona State Univ Dept Elect Engn Tempe AZ 85287 USA

ISBN: (纸本)0780385047

In this paper, we address the problem of designing battery-friendly packet transmission policies for wireless data transmission. Our objective is to maximize the lifetime of battery for wireless devices subject to certain delay constraints. We present three packet transmission schemes and evaluate them with respect to battery performance. The first scheme based on combining multiple packets, utilizes the battery charge recovery due to long idle periods. The second scheme based on a modified version of lazy packet scheduling, draws lower current and is battery efficient. The third scheme which is based on a combination of the above two schemes, has superior battery performance at the expense of larger average packet delay. All three schemes were simulated for a wireless communication framework with internet traffic, and the results validated.

关键词： Telecommunication systems

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Synthesis and high level optimisation of multidimensional dataflow actor networks on FPGA

Synthesis and high level optimisation of multidimensional da...

引用

ieee workshop on signal processing systems design and implementation

作者： McAllister, J Woods, R Walke, R Reilly, D Queens Univ Belfast ECIT Belfast BT9 5EE Antrim North Ireland

ISBN: (纸本)0780385047

This paper presents a new dataflow graph based approach for modelling, rapidly implementing, and performing high level optimization of embedded systems including dedicated pipelined hardware components. This overcomes problems with current approaches which cannot achieve both pipelined circuit implementation and flexibility for high level optimization. A new dataflow modellng technique is presented, in conjunction with an enhanced component network synthesis approach. This technique is applied to a normalized lattice filter example demonstrating the capability for significant circuit performance improvements, a more intelligent directed synthesis flow and increased implementation flexibility.

关键词： multidimensional signal processing data flow graphs circuit optimisation field programmable gate arrays logic design embedded systems pipeline processing lattice filters high level optimisation multidimensional dataflow actor networks FPGA dataflow graphs embedded systems optimization dedicated pipelined hardware components dataflow modelling technique component network synthesis normalized lattice filter directed synthesis flow Field programmable gate arrays lattice filters Circuit optimization data flow graphs multidimensional signal processing Embedded systems Pipeline processing Logic design data flow

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VLSI map decoder architectural analysis

VLSI map decoder architectural analysis

引用

ieee workshop on signal processing systems design and implementation

作者： Elassal, M Bayoumi, M Univ Louisiana CACS Lafayette LA 70504 USA

ISBN: (纸本)0780385047

This paper presents an architectural analysis for the MAP decoder hardware implementations. The use of the graphical representation of the trellis-time graph is proposed to analytically model the scheduling between different computational operations. The ALAP schedule policy for the branch metric operations is used to minimize both the branch memory size and power consumption. In addition, key architecture metrics are derived from the analytical model. Finally, FPGA implementation of various architectures are presented.

关键词： maximum likelihood decoding turbo codes iterative decoding VLSI field programmable gate arrays maximum a posteriori decoding turbo coding VLSI MAP decoder decoder hardware implementation trellis-time graph graphical representation ALAP schedule policy branch metric operations branch memory size minimization power consumption minimization FPGA implementation Iterative decoding turbo codes Field programmable gate arrays maximum likelihood decoding Power consumption decoders

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ELMMA: A new low power high-speed adder for RNS

ELMMA: A new low power high-speed adder for RNS

引用

ieee workshop on signal processing systems design and implementation

作者： Patel, RA Benaissa, M Powell, N Boussakta, S Univ Sheffield Dept Elect & Elect Engn Sheffield S1 3JD S Yorkshire England

ISBN: (纸本)0780385047

Modular adders are fundamental arithmetic components that are employed in Residue Number System (RNS) based digital signal processing (DSP) systems. They are widely used in modular multipliers, residue to binary converters and in implementing other arithmetic operations such as scaling. In addition, increasing operating frequencies as well as a growing demand for portable electronics have brought power reduction to the forefront of modem day design methodologies. Thus, the design of power efficient modular adders is of great significance if RNS circuits are to be utilized in future DSP systems. In this paper, we propose a new modular adder that is based on the ELM addition algorithm. VLSI implementations using 0.13/mum standard-cell technology show that the proposed architecture not only exhibits power efficiency, but also delay x area efficiency when compared to existing modular adder designs in the literature.

关键词： adders residue number systems VLSI integrated circuit design network synthesis logic design power consumption digital signal processing chips high-speed adder modular adders arithmetic components residue number system RNS digital signal processing systems DSP systems modular multipliers residue to binary converters scaling power reduction VLSI implementations 0.13 micron residue number systems digital signal processing chips adders power reduction network synthesis Logic design integrated circuit design signal processing Worksystem Power consumption Modularity

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Efficient hardware realization of IRA code decoders

Efficient hardware realization of IRA code decoders

引用

ieee workshop on signal processing systems design and implementation

作者： Kienle, F Wehn, N Univ Kaiserslautern Microelect Syst Design Res Grp D-67663 Kaiserslautern Germany

ISBN: (纸本)0780385047

Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular Repeat-Accumulate (IRA) codes belong to the class of Low-Density Parity-Check (LDPC) codes and can even outperform the recently introduced Turbo-Codes of current communication standards. implementation complexity like area, achievable throughput of these channel coding schemes will have a major impact on the decision of standardization committees. In this paper we investigate implementation issues of IRA codes and analyze the strong interdependency of code performance and architectural dependencies, like throughput and area. We present an architecture template which is capable to decode hardware optimized IRA codes which can outperform Turbo-Codes (TC). We demonstrate this new approach through instances synthesized in a 0.13 mum technology.

关键词： decoding parity check codes channel coding LDPC codes linear-time encoding complexity encoder IRA code decoder hardware implementation irregular repeat-accumulate codes low-density parity-check codes implementation area achievable throughput hardware optimized IRA codes 0.13 micron Channel coding low density parity check codes parity check codes DECODING ENCODER Codes

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