A design for a White Gaussian Noise Generator (WGNG) is modified and implemented as a 0.18-μm CMOS digital ASIC for high-speed communication channel emulation. The original design was implemented using an FPGA. The g...
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This paper describes a high speed fully pipelined parallel architecture for the New Three Step Search (NTSS) block-matching algorithm for the estimation of small motions in video coding. Techniques for reducing extern...
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Minimising the energy consumption due to the data storage and transfer in data-dominated systems is critical for the design of embedded systems. Distributed memory organisations have been proposed as an efficient stor...
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New trends in wireless communication systems has dictated the need for dynamical adaptation of communication systems in order to suit enviromental requirements. The authors present a reformulation based VLSI architect...
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ISBN:
(纸本)0780385047
New trends in wireless communication systems has dictated the need for dynamical adaptation of communication systems in order to suit enviromental requirements. The authors present a reformulation based VLSI architecture for threhold selection for Adaptive Viterbi Decoding in wireless applications. Through reformulation of the Adaptive Viterbi Algorithm, the compare operation for threshold selection in Add Compare Select (ACS) unit is simplified from variable based to constant based and the width of path metric is reduced. The reformulated architecture results in a significant reduction of hardware complexity in both standard cell and Look Up Table (LUT) technologies. The paper describes the reformulation technique, its VLSI Architecture for Adaptive Viterbi Decoding and its implementations in both ASIC and FPGA technologies. We also demonstrate that in additon to significant reduction in data path complexity, there is also a 25% to 47% storage reduction in the Path Metric Memory Unit (PMU).
An MPEG-4 video coding SOC design is presented in this paper. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search ...
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This paper proposes a novel low power multiplier-less radix-4 Single-path Delay Commutator (R4SDC) FFT processor architecture for wireless LAN (ieee 802.11 standard) applications, where short FFTs are utilised in the ...
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A software based ieee 802.11a digital baseband transmitter has been implemented on a highly parallel single-chip DSP processor. The processing platform is a programmable and reconfigurable Asynchronous Array of simple...
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A High throughput fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) processor for double-rate wireless LAN based on double-rate OFDM communication systems is proposed. It is an efficiently pipelined rad...
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In this paper we present the hardware and software system architecture for a personal digital video player and recorder using a media processor and an MPEG-2 video codec.
ISBN:
(纸本)0780364880
In this paper we present the hardware and software system architecture for a personal digital video player and recorder using a media processor and an MPEG-2 video codec.
To satisfy the advanced FEC standard that performs both convolutional code and turbo code, a unified convolutional/turbo decoder is needed. In this paper, both timing of Viterbi and MAP algorithm are analyzed. We intr...
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