Reducing power consumption prolongs battery life and increases integration. In digital CMOS designs, switching activity is closely connected with the total power consumption. Switching activity on programmable process...
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A CMOS Image Sensor codenamed EYE2 developed on a standard Intel CMOS process and designed into the Intel 971 Camera Kit is described. EYE2 converted incident visual images into 10-bit digital data streams for still a...
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ISBN:
(纸本)0780364880
A CMOS Image Sensor codenamed EYE2 developed on a standard Intel CMOS process and designed into the Intel 971 Camera Kit is described. EYE2 converted incident visual images into 10-bit digital data streams for still and video imaging applications. The analog signalprocessing essential to achieving the very high SNR desired is detailed. A fully differential architecture was implemented In order to achieve a desired SNR of 60dB with known techniques [1]...[6] for the minimization of signal degradation. Novel techniques implemented helped speedup the analog signal path and reduce power consumption in the chip.
We propose a channel estimation technique based on an expectation maximization (EM) algorithm, for space-time block coded (STBC) multi-input njuldoutput (MIMO) OFDM systems. The channel estimation is done by decomposi...
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ISBN:
(纸本)9781424403820
We propose a channel estimation technique based on an expectation maximization (EM) algorithm, for space-time block coded (STBC) multi-input njuldoutput (MIMO) OFDM systems. The channel estimation is done by decomposing the superimposed received signals, into their signal components and estimating the channelparameters of each signal component separately.
To meet the real time requirements an interpolation free, parallel algorithm for the Fast Radon Transform (FRT) and Inverse FRT (IFRT) is proposed. The proposed method solves all the important problems associated with...
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To meet the real time requirements an interpolation free, parallel algorithm for the Fast Radon Transform (FRT) and Inverse FRT (IFRT) is proposed. The proposed method solves all the important problems associated with the previous interpolation free FRT and IFRT algorithm and reduces the number of computations and algorithmic complexities significantly. The proposed algorithm is highly regular and we also describe a methodology to design a dedicated parallel processing architecture from the view point of its efficient implementation.
This paper suggests an automated validation approach in testing advanced digital signalprocessing algorithms. These algorithms, which are intended for the implementation of the base band processor of Software defined...
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ISBN:
(纸本)9781424403820
This paper suggests an automated validation approach in testing advanced digital signalprocessing algorithms. These algorithms, which are intended for the implementation of the base band processor of Software defined radios, are developed in software (Digital signal Processors DSP) and hardware (FP(;A) environments in order to meet real-time and offline requirements. The automation of the testing of such algorithms
In the center of our work lies an FPGA implementation of an iterative image restoration algorithm. Our work presents an initial analysis of the algorithm as well as modifications made on the algorithm during the adapt...
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ISBN:
(纸本)0780364880
In the center of our work lies an FPGA implementation of an iterative image restoration algorithm. Our work presents an initial analysis of the algorithm as well as modifications made on the algorithm during the adaptation onto reconfigurable platform. We are presenting our hardware design for the image restoration algorithm and our estimations on the performance of the FPGA implementation. Our results show that the speedup gained for practical systems varies between 6.5 and 10.2 for different images. In this paper we are also proposing and evaluating a statistical method for analysis of images subject to restoration to gain insight into the convergence time of the restoration algorithm. Based on this we explored a image partitioning strategy using this statistical analysis.
Portable systems today are designed with lowering the energy consumption as the primary design metric. This is unfortunate since maximizing battery lifetime is. a more appropriate metric, and lowering energy does not ...
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ISBN:
(纸本)0780377958
Portable systems today are designed with lowering the energy consumption as the primary design metric. This is unfortunate since maximizing battery lifetime is. a more appropriate metric, and lowering energy does not necessarily mean improving battery lifetime. In this paper we first show how to design battery-friendly implementations of common signalprocessing kernels such as FIR filters and FFT. The basic idea is to generate a load profile that results in better battery behavior. Next, we demonstrate how frequency scaling can be used effectively to improve the battery behavior of an application such as MPEG2.
The authors present a low power and area efficient turbo soft-input soft-output (SISO) decoder based on two-step soft-output Viterbi algorithm (SOVA) targeting wireless mobile communication systems. Our turbo SISO dec...
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ISBN:
(纸本)0780393333
The authors present a low power and area efficient turbo soft-input soft-output (SISO) decoder based on two-step soft-output Viterbi algorithm (SOVA) targeting wireless mobile communication systems. Our turbo SISO decoder is based on trace back algorithm (TBA) and saves area and power by replacing the FIFO memory with an additional transition metric unit (TMU). The paper presents the implementation of SOVA decoder for constraint lengths K=3, 4, and 5, describing the design methodology and evaluation environment. Simulation results are provided showing up to 20% power saving and 46% area saving compared to a conventional SOVA decoder implementation.
This paper deals with the design and implementation on FPGA of an intermediate frequency transceiver for OFDM-based WLAN. The circuit has been particularized for Hiperlan 2 standard, but most of the work can be genera...
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A novel Wireless Local Area Network (WLAN) security processor is described in this paper. This processor is capable of offloading all security encapsulation in an ieee 802.11i compliant Medium Access Control (MAC) lay...
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