Heterodyne filters provide both tunable and adaptive filters with applications in narrow-band interference attenuation for spread-spectrum and other broad-band communications systems. A new complex-arithmetic version ...
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ISBN:
(纸本)0780377958
Heterodyne filters provide both tunable and adaptive filters with applications in narrow-band interference attenuation for spread-spectrum and other broad-band communications systems. A new complex-arithmetic version of the tunable heterodyne filter offers significant hardware savings over previous versions and can more easily be implemented in adaptive filter applications.
FPGA-based DSP generally has two aspects: processing pipelines and finite state machine (FSM) controllers. implementation of these components are typically one of the more challenging parts of the project that often t...
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ISBN:
(纸本)9781538663189
FPGA-based DSP generally has two aspects: processing pipelines and finite state machine (FSM) controllers. implementation of these components are typically one of the more challenging parts of the project that often takes a significant portion of development time. Furthermore, it is a part of the code that may be the limiting factor in system performance. The ALCHA language is a new programming language for coding FPGA firmware that is currently under development. ALCHA focuses on providing a variety of powerful features that will improve developer productivity. This paper presents ALCHA features that aim to support the two DSP features mentioned above. Pipelining is facilitated by letting the developer write code in terms of real-world units, such as voltage, metres and radians. The implementation of FSM controllers is supported by using a structured procedural programming model to express algorithm flow. The programming model has been designed with object-orientation in mind so that the ALCHA user can make use of polymorphism and other abstraction mechanisms.
In this paper, we consider an application of an iterative decorrelating receiver to direct sequence ultra wideband (DS-UWB) multiple access systems, which utilize biphase modulation. As the number of users increases i...
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The architecture for EBCOT in JPEG 2000 is presented. The architecture embeds all functions necessary to produce the final codestream consistent with the JPEG 2000 specification. A number of hardware optimisation meth...
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ISBN:
(纸本)0780393333
The architecture for EBCOT in JPEG 2000 is presented. The architecture embeds all functions necessary to produce the final codestream consistent with the JPEG 2000 specification. A number of hardware optimisation methods are used to achieve the high throughput at relatively low cost of hardware resources. The architecture is verified in simulations and synthesized for ASIC and FPGA technologies. implementation results for FPGA Stratix II devices show that it can work at 120 MHz and process about 40 million samples per second in the regular lossless mode.
The paper describes an MPEG-2 audio decoder applied in multichannel extension. In the analysis of intelligent implementation strategy, the decoder can be divided into two hardware-oriented architecture stages. Also, a...
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The paper describes an MPEG-2 audio decoder applied in multichannel extension. In the analysis of intelligent implementation strategy, the decoder can be divided into two hardware-oriented architecture stages. Also, an efficient architecture for multichannel processor is presented. The decoder is developed for the approach for simplicity and low-cost design.
This paper discusses the optimization of the H.264/AVC sub-pixel interpolation operation in the context of a software implementation on a subword parallel processor. Several known algorithmic and architectural optimiz...
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ISBN:
(纸本)0780393333
This paper discusses the optimization of the H.264/AVC sub-pixel interpolation operation in the context of a software implementation on a subword parallel processor. Several known algorithmic and architectural optimization approaches are combined to achieve a low-cost interpolation implementation. The proposed interpolation scheme, which produces identical results with the reference software, requires no multiplications and 16-bit integer arithmetic is sufficient for the computation. The instruction set extensions result in cycle savings without much increasing the hardware cost. They also enable in-place processing in the half-pixel interpolation. When the optimizations are applied, it is possible to implement the H.264/AVC decoder without a multiplier.
In this paper, a novel architecture for the implementation of Serial Parallel Multipliers (SPM) is proposed. The proposed multiplier is based on a segmentation technique of a simple SPM to blocks of equal bit length. ...
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ISBN:
(纸本)0780393333
In this paper, a novel architecture for the implementation of Serial Parallel Multipliers (SPM) is proposed. The proposed multiplier is based on a segmentation technique of a simple SPM to blocks of equal bit length. This multiplier achieves higher throughput because it requires small number of zeros to start a new multiplication cycle at a moderate hardware expense and achieves significant hardware reduction compared to the Double Precision SPM. The proposed technique permits the optimization of the area time product.
In this paper, we describe a novel algorithm for modular exponentiation of large integers and present its hardware implementation. This algorithm combines elements from Montgomery's modular multiplication techniqu...
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ISBN:
(纸本)0780393333
In this paper, we describe a novel algorithm for modular exponentiation of large integers and present its hardware implementation. This algorithm combines elements from Montgomery's modular multiplication technique, carry-save and carry-delayed number representations. The major advantage of this algorithm over previously reported algorithms is that it does not require the result of each modular multiplication in the exponentiation process to be converted from the redundant representation back to a nonredundant form. In our algorithm, the conversion is only necessary at the end of all the modular multiplications. Avoiding the conversion speeds up the modular exponentiation process. In addition, the algorithm allows for a fast, modular, and scalable hardware implementation.
An approach to the realisation of 2D FIR filters based on a novel radix-differential arithmetic is introduced. The differential algorithm is accomplished by coding the input video signal more efficiently using a DPCM ...
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ISBN:
(纸本)0780338065
An approach to the realisation of 2D FIR filters based on a novel radix-differential arithmetic is introduced. The differential algorithm is accomplished by coding the input video signal more efficiently using a DPCM coding system. Whereas the filter's coefficients are fed in digit serial fashion and specified using radix-2(n) arithmetic. The proposed approach provides a spectrum of architectures to allow a more flexible design trade off analysis between throughput rate and hardware cost.
As wireless communications advances, the complexity of waveform processing places an ever increasing demand on baseband processing resources. As this is a difficult problem for traditional processing solutions to addr...
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