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检索条件"任意字段=2005 ACM SIGPLAN Symposium on Principles and Practise of Parallel Programming, PROPP 05"

共 12 条记录，以下是1-10 订阅

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Proceedings of the 2005 acm sigplan symposium on principles and Practice of parallel programming, PPOPP'05

Proceedings of the 2005 ACM SIGPLAN Symposium on Principles ...

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2005 acm sigplan symposium on principles and practise of parallel programming, propp 05

The proceedings contain 28 records. The topics discussed include: compiler techniques for high performance sequentially consistent Java programs;effective communication coalescing for data-parallel applications;a linear-time algorithm for optimal barrier placement;composable memory transactions;static analysis of atomicity for programs with non-blocking synchronization;revocable locks for non-blocking programming;automated type-based analysis of data races and atomicity;scaling model checking of dataraces using dynamic information;a novel approach for partitioning iteration spaces with variable densities;applications of synchronization coverage;and fault tolerant high performance computing by a coding approach.

关键词： parallel processing systems

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Effective communication coalescing for data-parallel applications

Effective communication coalescing for data-parallel applica...

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2005 acm sigplan symposium on principles and practise of parallel programming, propp 05

作者： Chavarría-Miranda, Daniel Mellor-Crummey, John Dept. of Computer Science Rice University

Communication coalescing is a static optimization that can reduce both communication frequency and redundant data transfer in compiler-generated code for regular, data parallel applications. We present an algorithm for coalescing communication that arises when generating code for regular, data-parallel applications written in High Performance Fortran (HPF). To handle sophisticated computation partitionings, our algorithm normalizes communication before attempting coalescing. We experimentally evaluate our algorithm, which is implemented in the dHPF compiler, in the compilation of HPF versions of the NAS application benchmarks SP, BT and LU. Our normalized coalescing algorithm improves the performance and scalability of compiler-generated code for these benchmarks by reducing the communication volume up to 55% compared to a simpler coalescing strategy and enables us to match the communication volume and frequency in hand-optimized MPI implementations of these codes. Copyright 2005 acm.

关键词： parallel processing systems

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Performance modeling and optimization of parallel out-of-core tensor contractions 05

Performance modeling and optimization of parallel out-of-cor...

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2005 acm sigplan symposium on principles and practise of parallel programming, propp 05

作者： Gao, Xiaoyang Sahoo, Swarup Kumar Lam, Chi-Chung Ramanujam, J. Lu, Qingda Baumgartner, Gerald Sadayappan, P. Dept. of Computer Science and Engineering Ohio State University Dept. of Computer Science Louisiana State University Dept. of Electrical and Computer Engineering Louisiana State University

ISBN: (纸本)9781595930804

The Tensor Contraction Engine (TCE) is a domain-specific compiler for implementing complex tensor contraction expressions arising in quantum chemistry applications modeling electronic structure. This paper develops a performance model for tensor contractions, considering both disk I/O as well as inter-processor communication costs, to facilitate performance-model driven loop optimization for this domain. Experimental results are provided that demonstrate the accuracy and effectiveness of the model. Copyright 2005 acm.

关键词： parallel processing systems

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Why is graphics hardware so fast? 05

Why is graphics hardware so fast?

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2005 acm sigplan symposium on principles and practise of parallel programming, propp 05

作者： Hanrahan, Pat Stanford University Gates Computer Science Building Stanford CA 94305-4070 Department of Computer Science and Electrical Engineering Stanford University

ISBN: (纸本)9781595930804

NVIDIA has claimed that their graphics processors (or GPUs) are improving at a rate three times faster than Moore's Law for processors. A $25 GPU is rated from 50-100 gigaflops and approximately 1 teraop (8-bit ops). Alongside this increase in performance is new functionality. The most recent innovation is user-programmable vertex and fragment stages that allow GPUs to compute a wide range of new visual effects enabling movie-quality games. Announced chips have as many as 200 programmable floating point units operating in parallel. The result is that the latest generation of commodity graphics and game chips are powerful data-parallel computers. Why are these graphics processors so fast? Will the future performance of GPUs continue to increase faster than CPUs? Can these GPUs be used for scientific computing? And, if so, how might they be programmed?

关键词： parallel processing systems

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A sampling-based framework for parallel data mining 05

A sampling-based framework for parallel data mining

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2005 acm sigplan symposium on principles and practise of parallel programming, propp 05

作者： Cong, Shengnan Han, Jiawei Hoeflinger, Jay Padua, David Department of Computer Science University of Illinois Urbana IL 61801 United States KAI Software Lab. Intel Americas Inc. Champaign IL 61820 United States

ISBN: (纸本)9781595930804

The goal of data mining algorithm is to discover useful information embedded in large databases. Frequent itemset mining and sequential pattern mining are two important data mining problems with broad applications. Perhaps the most efficient way to solve these problems sequentially is to apply a pattern-growth algorithm, which is a divide-and-conquer algorithm [9, 10]. In this paper, we present a framework for parallel mining frequent itemsets and sequential patterns based on the divide-and-conquer strategy of pattern growth. Then, we discuss the load balancing problem and introduce a sampling technique, called selective sampling, to address this problem. We implemented parallel versions of both frequent iternsets and sequential pattern mining algorithms following our framework. The experimental results show that our parallel algorithms usually achieve excellent speedups. Copyright 2005 acm.

关键词： parallel processing systems

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Static analysis of atomicity for programs with non-blocking synchronization 05

Static analysis of atomicity for programs with non-blocking ...

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2005 acm sigplan symposium on principles and practise of parallel programming, propp 05

作者： Wang, Liqiang Stoller, Scott D. Department of Computer Science State University of New York at Stony Brook Stony Brook NY 11794 United States

ISBN: (纸本)9781595930804

In concurrent programming, non-blocking synchronization is very efficient but difficult to design correctly. This paper presents a static analysis to show that code blocks are atomic, i.e., that every execution of the program is equivalent to one in which those code blocks execute without interruption by other threads. Our analysis determines commutativity of operations based primarily on how synchronization primitives (including locks, load-linked, store-conditional, and compare-and-swap) are used. A reduction theorem states that certain patterns of commutativity imply atomicity. Atomicity is itself an important correctness requirement for many concurrent programs. Furthermore, an atomic code block can be treated as a single transition during subsequent analysis of the program;this can greatly improve the efficiency of the subsequent analysis. We demonstrate the effectiveness of our approach on several concurrent non-blocking programs. Copyright 2005 acm.

关键词： parallel processing systems

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Extracting SMP parallelism for dense linear algebra algorithms from high-level specifications 05

Extracting SMP parallelism for dense linear algebra algorith...

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2005 acm sigplan symposium on principles and practise of parallel programming, propp 05

作者： Low, Tze Meng Van De Geijn, Robert A. Van Zee, Field G. Department of Computer Sciences University of Texas at Austin Austin TX 78712

ISBN: (纸本)9781595930804

We show how to exploit high-level information, available as part of the derivation of provably correct algorithms, so that SMP parallelism can be systematically identified. Recent research has shown that loop-based dense linear algebra algorithms can be systematically derived from the mathematical specification of the operation. Fundamental to the methodology is the determination of loop-invariants (in the sense of Dijkstra and Hoare) from which correct loops can be systematically derived. We show how the high-level specification of the operation together with these loop-invariants can be exploited to detect the independence of loop iterations. This in turn then allows a Workqueuing Model to be used to implement and parallelize the algorithms using a feature proposed for OpenMP 3.0, task queues. Although performance is not the main feature of this paper, performance is reported on a 4 CPU Itanium2 server for a concrete example, the symmetric rank-k update operation. Copyright 2005 acm.

关键词： parallel processing systems

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A novel approach for partitioning iteration spaces with variable densities 05

A novel approach for partitioning iteration spaces with vari...

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2005 acm sigplan symposium on principles and practise of parallel programming, propp 05

作者： Kejariwal, Arun Nicolau, Alexandra Banerjee, Utpal Polychronopoulos, Constantine D. Center for Embedded Computer Systems University of California at Irvine Irvine CA United States Intel Corporation Santa Clara CA United States Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign Urbana IL United States

ISBN: (纸本)9781595930804

Efficient partitioning of parallel loops plays a critical role in high performance and efficient use of multiprocessor systems. Although a significant amount of work has been done in partitioning and scheduling of loops with rectangular iteration spaces, the problem of partitioning non-rectangular iteration spaces - e.g., triangular, trapezoidal iteration spaces - with variable densities has not been addressed so far to the best of our knowledge. In this paper, we present a mathematical model for partitioning N-dimensional non-rectangular iteration spaces with variable densities. We present a unimodular loop transformation and a geometric approach for partitioning an iteration space along an axis corresponding to the outermost loop across a given number of processors to achieve near-optimal performance, i.e., to achieve nearoptimal load balance across different processors. We present a case study to illustrate the effectiveness of our approach. Copyright 2005 acm.

关键词： parallel processing systems

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An evaluation of global address space languages: Co-array fortran and Unified parallel C 05

An evaluation of global address space languages: Co-array fo...

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2005 acm sigplan symposium on principles and practise of parallel programming, propp 05

作者： Coarfa, Cristian Dotsenko, Yuri Mellor-Crummey, John Cantonnet, François Ei-Ghazawi, Tarek Mohanti, Ashrujit Yao, Yiyi Chavarría-Miranda, Daniel Rice University Houston TX George Washington University Washington DC Pacific Northwest National Laboratory Richland WA

ISBN: (纸本)9781595930804

Co-array Fortran (CAP) and Unified parallel C (UPC) are two emerging languages for single-program, multiple-data global address space programming. These languages boost programmer productivity by providing shared variables for inter-process communication instead of message passing. However, the performance of these emerging languages still has room for improvement. In this paper, we study the performance of variants of the NAS MG, CG, SP, and BT benchmarks on several modern architectures to identify challenges that must be met to deliver top performance. We compare CAF and UPC variants of these programs with the original Fortran+MPI code. Today, CAF and UPC programs deliver scalable performance on clusters only when written to use bulk communication. However, our experiments uncovered some significant performance bottlenecks of UPC codes on all platforms. We account for the root causes limiting UPC performance such as the synchronization model, the communication efficiency of strided data, and source-to-source translation issues. We show that they can be remedied with language extensions, new synchronization constructs, and, finally, adequate optimizations by the back-end C compilers. Copyright 2005 acm.

关键词： Computer programming languages

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Exposing speculative thread parallelism in SPEC2000 05

Exposing speculative thread parallelism in SPEC2000

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2005 acm sigplan symposium on principles and practise of parallel programming, propp 05

作者： Prabhu, Manohar K. Olukotun, Kunle Stanford University Computer Systems Laboratory Stanford CA 94305

ISBN: (纸本)9781595930804

As increasing the performance of single-threaded processors becomes increasingly difficult, consumer desktop processors are moving toward multi-core designs. One way to enhance the performance of chip multiprocessors that has received considerable attention is the use of thread-level speculation (TLS). As a case study, we manually parallelized several of the SPEC CPU2000 floating point and integer applications using TLS. The use of manual parallelization enabled us to apply techniques and programmer expertise that are beyond the current capabilities of automated parallelizers. With the experience gained from this, we provide insight into ways to aggressively apply TLS to parallelize applications for high performance. This information can help guide future advanced TLS compiler design. For each application, we discuss how and where parallelism was located within the application, the impediments to extracting this parallelism using TLS, and the code transformations that were required to overcome these impediments. We also generalize these experiences to a discussion of common hindrances to TLS parallelization, and describe methods of programming that help expose application parallelism to TLS systems. These guidelines can assist developers of uniprocessor programs to create applications that can easily port to TLS systems and yield good performance. By using manual parallelization on SPEC2000, we provide guidance on where thread-level parallelism exists in these well known benchmarks, what limits its extraction, how to reduce these limitations and what performance can be expected on these applications from a chip multiprocessor system with TLS. Copyright 2005 acm.

关键词： parallel processing systems

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