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检索条件"任意字段=2005 International Conference on Field Programmable Logic and Applications, FPL"

共 1851 条记录，以下是31-40 订阅

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fpl Demo: 400G FPGA Packet Capture Based on Network Development Kit 32

FPL Demo: 400G FPGA Packet Capture Based on Network Developm...

引用

32nd international conference on field-programmable logic and applications (fpl)

作者： Cabal, Jakub Sikora, Jiri Friedl, Stepan Spinler, Martin Korenek, Jan CESNET Ale Zikova 4 Prague 16000 Czech Republic

ISBN: (纸本)9781665473903

CESNET, the Czech NREN (National Research and Education Network), has a long research history in the area of high-speed network monitoring using FPGA accelerated cards. Now, we are ready to present our open-source Network Development Kit for FPGAs1, which is ready for 400 Gbps data transfers via Ethernet and PCI Express. The demo aims to show the possibilities of NDK, which allows users to quickly and easily develop new network applications for FPGA-based acceleration cards. Even high-speed DMA Module fully supported in NDK is available free of charge for academic purposes. It can thus significantly contribute to the spread of 400G technology in the academic community and also among other users. The accelerator card equipped with the Intel Agilex I-Series FPGA will transmit and receive back 400G Ethernet (400GBASE) traffic via external loopback. The received packets will be forwarded via very fast packet DMA transfers directly to the RAM of the host computer.

关键词： field programmable gate arrays (FPGA)

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Ultra-Flow: An Ultra-fast and High-quality Optical Flow Accelerator with Deep Feature Matching on FPGA 32

Ultra-Flow: An Ultra-fast and High-quality Optical Flow Acce...

引用

32nd international conference on field-programmable logic and applications (fpl)

作者： Ling, Yehua Yan, Yuanxing Huang, Kai Chen, Gang Sun Yat Sen Univ Sch Comp Sci & Engn Guangzhou Guangdong Peoples R China Peng Cheng Lab Shenzhen Guangdong Peoples R China

ISBN: (纸本)9781665473903

Dense and accurate optical flow estimation is an important requirement for dynamic scene perception in autonomous systems. However, most of the existing FPGA accelerators are based on classic methods, which cannot deal with large displacements of moving objects in ultra-fast scenes. In this paper, we present Ultra-Flow, an ultra-fast pipelined architecture for efficient optical flow estimation and refinement. Ultra-Flow utilizes binary neural networks to generate the robust feature map, on which hierarchical matching is directly performed. Therefore, multiple usages of neural networks at hierarchical levels can be avoided to achieve hardware efficiency in Ultra-Flow. Optimizations, including local flow regularization and enhanced matching, are further used to improve the throughput and refine the optical flow to obtain higher accuracy. Evaluation results show that, compared to state-of-the-art FPGA accelerators, Ultra-Flow achieves leading accuracy in the Middlebury sequences at ultra-fast processing speed up to 687.92 frames/s for 640x 480 pixel images.

关键词： field programmable gate arrays (FPGA)

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TRAC: Compilation-based Design of Transformer Accelerators for FPGAs 32

TRAC: Compilation-based Design of Transformer Accelerators f...

引用

32nd international conference on field-programmable logic and applications (fpl)

作者： Plagwitz, Patrick Hannig, Frank Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci Nurnberg Germany

ISBN: (纸本)9781665473903

Transformer-type Neural Networks (NNs) have shown impressive accuracy numbers in Natural Language Processing (NLP) applications where Recurrent Neural Networks (RNNs) have been in use before, even surpassing them. However, differing considerably from common types of NNs, existing accelerator designs, particularly for field-programmable Gate Arrays (FPGAs), cannot be used to implement them. Previous research has shown FPGAs to be platforms superior to CPUs and even GPUs for accelerating NNs when it comes to energy efficiency. Following the development of automated compiler-based design flows for NNs, there is still a lack of such an approach for transformers and FPGA targets. In this realm, this paper presents a novel compiler called TRAC as well as a library of operators and modules for implementing transformer accelerators on FPGAs. Based on optimization and code generation settings in the compiler using an integrated approach combining weight compression techniques with according adaptations of the accelerator modules, a design space of accelerators is defined and explored. For each design, a system-level data path and control unit architecture is generated, which integrates module-level designs using hierarchical High-Level Synthesis (HLS). We evaluate our implementation for the BERT network and provide results regarding the trade-off between execution time, accuracy, and FPGA resource usage.

关键词： field programmable gate arrays (FPGA)

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FRA-FPGA: Fast Reconfigurable Automata Processing on FPGAs 32

FRA-FPGA: Fast Reconfigurable Automata Processing on FPGAs

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32nd international conference on field-programmable logic and applications (fpl)

作者： Zhang, Peng Zhang, Shijun Li, Shang Zhang, Jin Liu, Shaoxun Bu, Youjun Southeast Univ Sch Cyber Sci & Engn Nanjing Peoples R China Purple Mt Labs Endogenous Safety & Secur Res Ctr Nanjing Peoples R China Natl Digital Switching Engn & Technol Res Ctr Zhengzhou Peoples R China

ISBN: (纸本)9781665473903

Accelerating regular expression (regex) matching, or equivalently finite automata processing, using FPGAs is widely adopted by many demanding regex-based applications to improve throughput and power efficiency. However, offloading a large regex rule set entirely into an FPGA is expensive, if not unaffordable, due to the limited on-chip resources. In this paper, we propose FRA-FPGA (Fast Reconfigurable Automata on FPGAs), a homogeneous NFA architecture on FPGAs which can be reconfigured within 1 mu s. Meanwhile, the reconfiguration time of FRA-FPGA is independent of the number of regex rules it accommodates. Because FRA-FPGA can be reloaded quickly, it is feasible to offload the small subset of activated regex rules into FRA-FPGA dynamically, as opposed to compiling the whole regex rule set into FPGA beforehand. We implemented FRA-FPGA on the Xilinx U200 card to accelerate Hyperscan. Our experimental results show that the FRA-FPGA can improve Hyperscan's throughput by about 15 times (stream mode) and 33 times (block mode), respectively, while consuming only 4.23% logic resources and 16.64% memory resources of the FPGA(VU9P).

关键词： field programmable gate arrays (FPGA)

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RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices 32

RAD-Sim: Rapid Architecture Exploration for Novel Reconfigur...

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32nd international conference on field-programmable logic and applications (fpl)

作者： Boutros, Andrew Nurvitadhi, Eriko Betz, Vaughn Univ Toronto Toronto ON Canada Vector Inst AI Toronto ON Canada Intel Corp Programmable Solut Grp N York ON Canada

ISBN: (纸本)9781665473903

With the continued growth in field-programmable gate array (FPGA) capacity and their incorporation into new environments such as datacenters, we have witnessed the introduction of a new class of reconfigurable acceleration devices (RADs) that go beyond conventional FPGA architectures. These devices combine a reconfigurable fabric with coarse-grained domain-specialized accelerator blocks all connected via a high-performance packet-switched network-on-chip (NoC) for efficient system-wide communication. However, we lack the tools necessary to efficiently explore the huge design space for RADs, study the complex interactions between their different components and evaluate various combinations of design choices. In this work, we develop RAD-Sim, a cycle-level architecture simulator that allows rapid application-driven exploration of the design space of novel RADs. To showcase the capabilities of RAD-Sim, we map and simulate a state-of-the-art deep learning (DL) inference overlay on a RAD instance incorporating an FPGA fabric and a complex of hard matrix-vector multiplication engines, communicating over a system-wide NoC. Through this example, we show how RAD-Sim can help architects quantify the effect of changing specific architecture parameters on end-to-end application performance.

关键词： FPGA NoC accelerator blocks architecture simulator deep learning

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DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks 32

DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DS...

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32nd international conference on field-programmable logic and applications (fpl)

作者： Sommer, Jan Oezkan, M. Akif Keszocze, Oliver Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg D-91054 Erlangen Germany

ISBN: (纸本)9781665473903

The number of Digital Signal Processor (DSP) resources available in field programmable Gate Arrays (FPGAs) is often quite limited. Therefore, full utilization of available DSP resources for the computationally intensive parts of an algorithm is paramount for optimizing the non-functional properties of an implementation (i.e., performance, power, and area). The DSPs available in Xilinx devices implement large bit width operators (i.e. a 48-bit accumulator or a 18 x 27 multiplier). However, using such a DSP for low-precision quantized data (as is common in image processing or machine learning applications) leaves the DSP resources underutilized. As a remedy, a method has been proposed to pack and compute four 4-bit multiplications on a single DSP in a single clock cycle. This paper presents a generalization of this scheme to arbitrary bit widths and number of multiplications. We also demonstrate that the previously proposed approach leads to errors (Mean Absolute Error (MAE) = 0.37). Furthermore, we explain where these errors come from and how they can be corrected. On top, we introduce a novel approximate method called "Overpacking" which allows to squeeze even more multiplications into a single DSP at the cost of small errors (MAE = 0.47). Overpacking allows to squeeze six 4-bit multiplications into a single DSP compared to just four in the literature. Finally, we introduce an alternative method for packing multiple small-bit width additions into a single 48-bit accumulator for use in applications such as Spiking Neural Networks.

关键词： Digital Signal Processing (DSP) field-programmable Gate Array (FPGA) Approximate Computing

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Reduced-voltage OmpSs@FPGA: A Demonstration 31

Reduced-voltage OmpSs@FPGA: A Demonstration

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31st international conference on field-programmable logic and applications (fpl)

作者： Bacardit, Marc Perello Salami, Behzad Barcelona Supercomp Ctr Barcelona Spain

ISBN: (纸本)9781665437592

FPGAs are known for their flexibility compared to ASICs. While FPGAs are also attractive in regards to energy efficiency compared to GPUs and CPUs, they are not as energy efficient as ASICs due to the overhead of the programmable logic compared to a direct hardware implementation. FPGAs are at least an order of magnitude less energy-efficient than ASICs [1]. Undervolting (i.e., reducing the supply voltage below the nominal level) is an effective technique to mitigate this gap [2]–[6]. However, the procedure for undervolting in FPGAs is complex and device-dependent.

关键词： Voltage Energy efficiency Hardware field programmable gate arrays

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HiPReP: High-Performance Reconfigurable Processor - Architecture and Compiler 31

HiPReP: High-Performance Reconfigurable Processor - Architec...

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31st international conference on field-programmable logic and applications (fpl)

作者： Kasgen, Philipp Messelka, Mohamed Weinhardt, Markus Osnabruck Univ Appl Sci Fac Engn & Comp Sci Osnabruck Germany

ISBN: (纸本)9781665437592

The computational parallelism and energy efficiency inherent in reconfigurable hardware architectures like finegrained field-programmable Gate Arrays (FPGAs) and Coarse-Grained Reconfigurable Arrays (CGRAs) have been a subject of research mostly for Multimedia applications for many years [1]. The said strengths of reconfigurable systems are also beneficial for other application domains, e.g. High-Performance Computing (HPC), since single-core and multicore systems may soon hit scaling limits.

关键词： Multicore processing Computer architecture Parallel processing Hardware Energy efficiency Computational efficiency field programmable gate arrays

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Taping out an FPGA in 24 hours with OpenFPGA: The SOFA Project 31

Taping out an FPGA in 24 hours with OpenFPGA: The SOFA Proje...

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31st international conference on field-programmable logic and applications (fpl)

作者： Tang, Xifan Gore, Ganesh Brown, Grant Gaillardon, Pierre-Emmanuel Univ Utah Lab NanoIntegrated Syst LNIS Salt Lake City UT 84112 USA

ISBN: (纸本)9781665437592

This paper highlights the Skywater Open-source embedded FpgAs (SOFA) project, which is a series of open-source embedded FPGA IPs built with the Skywater 130nm technology. The SOFA project showcases an agile prototyping methodology for FPGAs, enabled by the OpenFPGA framework, whose fabrication-ready layouts are generated in 24 hours. We also present the associated Verilog-to-Bitstream toolchain for end users. [GRAPHICS] .

关键词： Layout Hardware design languages field programmable gate arrays Open source software

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Pharos: a Multi-FPGA Performance Monitor 31

Pharos: a Multi-FPGA Performance Monitor

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31st international conference on field-programmable logic and applications (fpl)

作者： Rafii, Arzhang Sun, Welson Chow, Paul Univ Toronto Dept Elect & Comp Engn Toronto ON Canada Alibaba Grp San Jose CA USA

ISBN: (纸本)9781665437592

In recent years, there has been a lot of focus on tools that help the development of FPGA applications. However, unlike the software world, there are not many FPGA tools that help analyze the performance of FPGA applications. Also, as the application platforms scale from one FPGA to many FPGAs, such as the well-known Microsoft Catapult platform, it is no longer feasible to rely on low-level FPGA debugging tools such as the embedded logic analyzers. We present Pharos, a lightweight, generic performance monitor for multi-FPGA systems. Pharos is capable of measuring unidirectional latency between multiple network -connected FPGAs, as well as measuring throughput and tracing events across the datacenter.

关键词： Protocols Debugging Tools Throughput Software field programmable gate arrays Monitoring

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