Microphone arrays are able to recognize, profile and locate sound-sources in noisy environments, but their quality is determined by the number of microphones. A higher number of microphones increases the computational...
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ISBN:
(纸本)9782839918442
Microphone arrays are able to recognize, profile and locate sound-sources in noisy environments, but their quality is determined by the number of microphones. A higher number of microphones increases the computational demand, making real-time response challenging. In this demo, we present a scalable and runtime reconfigurable architecture able to support a variable number of microphones and orientations in order to provide accurate sound-source localization in real-time.
Serverless computing has become a popular cloud computing paradigm. However, its deployment abstraction entails significant performance overheads. We explore the potential for enabling serverless computing on FPGAs an...
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ISBN:
(纸本)9798350341515
Serverless computing has become a popular cloud computing paradigm. However, its deployment abstraction entails significant performance overheads. We explore the potential for enabling serverless computing on FPGAs and present some early results that show the concurrency and scalability benefits on a stream processing workload. The FPGA enables flows of network data to flow directly into accelerators, which is beneficial for scenarios involving large packets and multiple request streams.
This PhD project aims to tackle the laborious design process of FPGA-based deep neural network (DNN) inference solutions by combining automatic machine learning (AutoML) algorithms with a compiler for custom-tailored ...
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ISBN:
(纸本)9798350341515
This PhD project aims to tackle the laborious design process of FPGA-based deep neural network (DNN) inference solutions by combining automatic machine learning (AutoML) algorithms with a compiler for custom-tailored dataflow accelerator architectures. Manual experiments on a first use case from the RadioML domain suggests great potential for joint optimization of DNN and accelerator, but emphasize the need for empirical quality-of-result (QoR) estimation models, which are the current focus of the project. Future work will entail design space modeling and evaluation of state-of-the-art exploration techniques.
Current networks are changing very fast. Network administrators need more flexible and powerful tools to be able to support new protocols or services very fast. The P4 language provides new level of abstraction for fl...
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ISBN:
(纸本)9789090304281
Current networks are changing very fast. Network administrators need more flexible and powerful tools to be able to support new protocols or services very fast. The P4 language provides new level of abstraction for flexible packet processing. Therefore, we have designed new architecture for memory efficient mapping of P4 match/action tables to FPGA. The architecture is based on DCFL algorithm and is able to balance the processing speed and available memory resources.
FPGAs are known for their flexibility compared to ASICs. While FPGAs are also attractive in regards to energy efficiency compared to GPUs and CPUs, they are not as energy efficient as ASICs due to the overhead of the ...
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ISBN:
(纸本)9781665437592
FPGAs are known for their flexibility compared to ASICs. While FPGAs are also attractive in regards to energy efficiency compared to GPUs and CPUs, they are not as energy efficient as ASICs due to the overhead of the programmablelogic compared to a direct hardware implementation. FPGAs are at least an order of magnitude less energy-efficient than ASICs [1]. Undervolting (i.e., reducing the supply voltage below the nominal level) is an effective technique to mitigate this gap [2]–[6]. However, the procedure for undervolting in FPGAs is complex and device-dependent.
The computational parallelism and energy efficiency inherent in reconfigurable hardware architectures like finegrained field-programmable Gate Arrays (FPGAs) and Coarse-Grained Reconfigurable Arrays (CGRAs) have been ...
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ISBN:
(纸本)9781665437592
The computational parallelism and energy efficiency inherent in reconfigurable hardware architectures like finegrained field-programmable Gate Arrays (FPGAs) and Coarse-Grained Reconfigurable Arrays (CGRAs) have been a subject of research mostly for Multimedia applications for many years [1]. The said strengths of reconfigurable systems are also beneficial for other application domains, e.g. High-Performance Computing (HPC), since single-core and multicore systems may soon hit scaling limits.
logic shrinkage is an open-source, state-of-the-art neural architecture search (NAS)-based approach to the automated design of DNN inference accelerators that ideally suit FPGA deployment [1], [2]. Where NAS tradition...
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Chromatic dispersion is one of the error sources limiting the transmission capacity in coherent optical communication that can be mitigated with digital signal processing. In this paper, the current status and plans o...
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ISBN:
(纸本)9781728199023
Chromatic dispersion is one of the error sources limiting the transmission capacity in coherent optical communication that can be mitigated with digital signal processing. In this paper, the current status and plans of implementation of chromatic dispersion compensation (CDC) filters on FPGAs are discussed. As these high-speed filters are most efficiently implemented in the frequency-domain, different approaches for high-speed FFT-based architectures are considered and preliminary results of fully parallel FFT implementation by utilizing FPGA hardware features are presented.
""The unique promise of embedded systems in FPGAs is that designers can develop and modify their own peripheral hardware with a high degree of flexibility. However, the task of verifying the hardware commonl...
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ISBN:
(纸本)9781479900046
""The unique promise of embedded systems in FPGAs is that designers can develop and modify their own peripheral hardware with a high degree of flexibility. However, the task of verifying the hardware commonly involves writing software to interact with it. T""
A ring oscillator physical unclonable function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabricati...
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ISBN:
(纸本)9789090304281
A ring oscillator physical unclonable function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabrication process to produce random outputs that are nevertheless stable across multiple measurements. Unfortunately, RO PUFs are known to be unstable especially when implemented on an fieldprogrammable Gate Array (FPGA). In this work, we comprehensively evaluate the RO PUF's stability on FPGAs, and we propose a phase calibration process to improve the stability of RO PUFs. The results show that the bit errors in our PUFs are reduced to less than 1%.
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