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Energy-Efficient Programable Analog Computing: Analog computing in a standard CMOS process

ieee solid-state circuits Magazine 2024年第4期16卷 32-40页

作者： Hasler, Jennifer Georgia Institute of Technology School of Electrical and Computer Engineering AtlantaGA30332 United States

When I started working on analog computing for neural network systems in the 1980s, the question everyone feared to be asked at the end of their presentation was "couldn't this be done on a DSP processor?"Carver Mead provided a theoretical and intuitive answer in 1990 that analog computing should be thousands of times more efficient than digital computation. Three decades later the "couldn't this be done on a DSP?"question, or its related question "couldn't this be done on a digital computing IC?", has been definitively addressed with a resounding No for several implementations. This paper addresses how end-to-end analog computing system demonstrates this increased efficiency over digital computing systems. These computations are possible entirely in a standard CMOS process using Floating-Gate (FG) devices available in any CMOS IC process. The efficiency is both at the computational circuit level, as well as at the architecture level. The first crossbar and single-transistor synapse concept appeared 30 years ago. The definitive demonstration of Mead's energy efficiency hypothesis appeared 20 years ago, and before that demonstration was the start of Compute in Memory (CiM) as well as the start of a large-scale FPAA with FG-enabled connections. Analog computing opportunities in Standard CMOS IC processes can provide many opportunities for the wider commercial market. © 2009-2012 ieee.

关键词： CMOS integrated circuits

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A 0.28V 80.9μW Transformer-Based DCO with 80kHz 1/f3 corner and 192.6dBc/Hz FoM

A 0.28V 80.9μW Transformer-Based DCO with 80kHz 1/f3 corner...

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ieee asian conference on solid-state circuits (asscc)

作者： Feng Gao Yuxiao Zhao Yulin Xie Zhongyuan Ying Hao Min State Key Laboratory of Integrated Chips and Systems Fudan University Shanghai China

ISBN: (数字)9798350376326

ISBN: (纸本)9798350376333

The power constraint of Internet of Things (IoT) nodes causes design challenges for the local oscillator of the transceiver, while the sub-0.5 V and sub- 0.1 mW oscillator design is becoming a trend [1–7]. The ultra-low-voltage (ULV), ultra-low-power (ULP) design of LC oscillators that provide a pure oscillation signal faces difficulty in start-up and amplitude [1].

关键词： Local oscillators Transformers Market research Transceivers solid state circuits Internet of Things Faces

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A 105.8dB A-weighted DR CT Delta-Sigma Audio ADC Using Current-Steering DAC Current Recycling Amplifier

A 105.8dB A-weighted DR CT Delta-Sigma Audio ADC Using Curre...

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ieee asian conference on solid-state circuits (asscc)

作者： Moo-Yeol Choi Myungjin Lee Minsung Kim Dongsu Kim Jongwoo Lee Samsung Electronics Hwaseong Korea

ISBN: (数字)9798350376326

ISBN: (纸本)9798350376333

Continuous-time (CT) delta-sigma modulators (DSMs) are attractive for audio ADCs due to their reduced bandwidth requirements of the op-amps and free to kT/C noise limitations as compared to the discrete-time (DT) counterparts. In these CT-DSMs, resistive DACs and current-steering DACs are widely used but the latter have advantages of better linearity characteristics and higher power supply rejection ratio (PSRR) without dedicated low-dropout regulator (LDO).

关键词： Regulators Power supplies Noise Linearity Bandwidth Delta-sigma modulation solid state circuits Recycling

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A 273.48 TOPS/W and 1.58 Mb/mm2 Analog-Digital Hybrid CIM Processor with Transpose Ternary-eDRAM Bitcell

A 273.48 TOPS/W and 1.58 Mb/mm2 Analog-Digital Hybrid CIM Pr...

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ieee asian conference on solid-state circuits (asscc)

作者： Hoichang Jeong Seungbin Kim Jeongmin Shin Keonhee Park Kyuho Jason Lee Ulsan National Institute of Science and Technology (UNIST)

ISBN: (数字)9798350376326

ISBN: (纸本)9798350376333

Deep neural network acceleration with Computing-in-Memory (CIM) processors [2–8] has been proposed to replace conventional computer architecture for high energy efficiency. However, previous CIM processors have struggled with the following limitations and challenges as shown in Fig. 1: 1) trade-off between cell density and computation linearity 2) trade-off between throughput degradation and analog-to-digital converter (ADC) area/power overheads, and 3) low system energy efficiency.

关键词： Program processors Microprocessors Linearity Computer architecture In-memory computing Throughput Energy efficiency Common Information Model (computing) solid state circuits Analog-digital conversion

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An 8.1-to-353 TOPS/W Energy-Aware Deep-Learning Accelerator Supporting Dynamic Neural Networks

An 8.1-to-353 TOPS/W Energy-Aware Deep-Learning Accelerator ...

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ieee asian conference on solid-state circuits (asscc)

作者： Ting-Yang Chen Yi-Lin Lo Tun-Yu Chang Chia-Hsiang Yang National Taiwan University Taipei Taiwan

ISBN: (数字)9798350376326

ISBN: (纸本)9798350376333

The demand for edge Al is rapidly increasing in various applications, including image classification, object detection, image segmentation, and key-point detection. Conventionally, deep-learning accelerators are designed for a fixed operating scenario, targeting a high accuracy with affordable energy consumption. However, the operating scenarios and performance requirements may vary. There are cases where low-energy operation is the first priority and a slight accuracy loss is tolerated. Therefore, an energy-aware solution supporting a variety of operating scenarios is required.

关键词： Image segmentation Energy consumption Accuracy Image edge detection Neural networks Object detection solid state circuits Image classification

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An Area-Efficient PVT-Dependent Adaptive Assist Termination Technique with SNM Detector for High Density SRAM

An Area-Efficient PVT-Dependent Adaptive Assist Termination ...

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ieee asian conference on solid-state circuits (asscc)

作者： Shunya Nagata Daiki Kitagata Kouji Satou Daisuke Nakamura Koji Tanaka Miki Tanaka Haruyuki Okuda Kenichiro Takiguchi Renesas Electronics Corporation Tokyo Japan

ISBN: (数字)9798350376326

ISBN: (纸本)9798350376333

This paper presents an area-efficient assist architecture using a static noise margin (SNM) detector for high-density (HD) SRAMs that are particularly vulnerable to process variation. The SNM detector is arranged in the peripheral and composed of a logic SRAM cell with simple small logic circuits that is designed to be a replica of the least stable cell in order to reproduce the worst SNM characteristics. By using this detector, unneeded assist can be eliminated depending on PVT conditions, as a result, dramatical improvement of access time (25%) and reduction of active power (24.4% @ write and 32.8% @read) are achieved with the smallest area overhead (0.015%).

关键词： Microprocessors Logic circuits Noise Detectors Computer architecture SRAM cells solid state circuits Logic

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A -60 to 145 °C, 216 fJ·K2 Energy-Efficient MOS-Based Temperature Sensor Achieving 71.8 mK Resolution

A -60 to 145 °C, 216 fJ·K2 Energy-Efficient MOS-Based Temp...

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ieee asian conference on solid-state circuits (asscc)

作者： Jooeun Kim Jeongmyeong Kim Minkyu Yang Kyounghun Kang Wanyeong Jung KAIST Daejeon Korea

ISBN: (数字)9798350376326

ISBN: (纸本)9798350376333

Energy-efficient temperature sensors are essential for on-chip temperature monitoring. To measure temperature, they convert temperature into electrical signals using devices such as MOSFETs [1], [2], BJTs [3], and resistors [4], [5]. MOS-based temperature sensors have low energy consumption because of their compact structures, but the energy efficiency has been relatively worse compared to recent resistor-based sensors. However, this low energy efficiency is not due to the intrinsic limitation of MOS devices. This paper optimizes the temperature conversion method and overall sensor design to improve the energy efficiency of MOS-based temperature sensors.

关键词： Temperature sensors Temperature measurement Resistors MOSFET Energy resolution Energy efficiency Sensors System-on-chip solid state circuits Monitoring

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22-nm Data Backup SRAM Using 3.3V IO MOSs with Ultralow-Voltage-Drop Erasure Technique for Secure IoT Applications

22-nm Data Backup SRAM Using 3.3V IO MOSs with Ultralow-Volt...

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ieee asian conference on solid-state circuits (asscc)

作者： Daiki Kitagata Shunya Nagata Kouji Satou Daisuke Nakamura Koji Tanaka Miki Tanaka Renesas Electronics Corporation Tokyo Japan

ISBN: (数字)9798350376326

ISBN: (纸本)9798350376333

A new erasure technique in terms of ultralow voltage drop is proposed for data backup SRAM (DBRAM). After a tampering event is detected, the proposed macro erases all of the data stored in cells for a short period equivalent to 3 cycles with the same peak current as that of the normal SRAM read and write operations. As a result, the DBRAM can achieve erasure function even in a limited power supply condition such as battery-operated loT devices. The power performances and peak current characteristics are computationally analyzed and experimentally verified using the fabricated test chips in 22 nm CMOS process.

关键词： Performance evaluation Power supplies Random access memory Voltage CMOS process solid state circuits Internet of Things

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A 300-GHz-Band 36-Gb/s Scalable 2x2 2D Phased-Array CMOS Receiver

A 300-GHz-Band 36-Gb/s Scalable 2x2 2D Phased-Array CMOS Rec...

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ieee asian conference on solid-state circuits (asscc)

作者： Satoshi Tanaka Shinsuke Hara Kyoya Takano Akifumi Kasamatsu Yoshiki Sugimoto Kunio Sakakibara Shunichi Kubo Takeshi Yoshida Shuhei Amakawa Minoru Fujishima Hiroshima University Japan National Institute of Information and Communications Technology Japan Tokyo University of Science Japan Nagoya Institute of Technology Japan THine Electronics Inc. Japan

Two-dimensional beamforming is a significant challenge for subterahertz transceivers. In this paper, we propose a two-dimensional beamforming receiver (RX) circuit that can be expanded to $n \times n$, and report the ... 详细信息

ISBN: (数字)9798350376326

ISBN: (纸本)9798350376333

关键词： Array signal processing Prototypes Receivers CMOS technology Transceivers solid state circuits

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A 3-D Ising Machine with 12-Way Supply-and-Bulk Injection Locking Oscillators for Combinatorial Problem Solving

A 3-D Ising Machine with 12-Way Supply-and-Bulk Injection Lo...

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ieee asian conference on solid-state circuits (asscc)

作者： Jiaer Chen Yingna Huang Jiamin Li Longyang Lin Han Wu Jerald Yoo National University of Singapore Singapore Southern University of Science and Technology China Seoul National University Seoul Korea

ISBN: (数字)9798350376326

ISBN: (纸本)9798350376333

Ising machine is an emerging quantum-inspired computing processor that quickly solves the combinatorial problem. Compared to quantum computers, CMOS Ising machine searches the ground or approximate lowest Hamiltonian energy at room temperature with much lower power consumption and a smaller form factor [1] –[7], [9], [10]. Nevertheless, the state-of-the-art CMOS Ising machine still faces challenges for solving real-world problems.

关键词： Computers Quantum computing Three-dimensional displays Temperature Power demand Injection-locked oscillators solid state circuits Land surface temperature Problem-solving Faces

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