The proceedings contain 126 papers. The topics discussed include: system-level design for FPGAs;adventures with a reconfigurable research platform;accelerating a medical 3D brain MRI analysis algorithm using a high-pe...
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ISBN:
(纸本)1424410606
The proceedings contain 126 papers. The topics discussed include: system-level design for FPGAs;adventures with a reconfigurable research platform;accelerating a medical 3D brain MRI analysis algorithm using a high-performance reconfigurable computer;floating-point trigonometric functions for FPGAs;a many-core implementation based on the reconfigurable mesh model;improving timing-driven FPGA packing with physical information;clock-aware placement for FPGAs;physical unclonable functions, FPGAs and public-key crypto for IP protection;FPGA implementation of a data-driven stochastic biochemical simulator with the next reaction method;a design methodology for communication infrastructures on partially reconfigurable FPGAs;dynamic voltage scaling in a FPGA-based system-on-chip;multiplexer-based routing fabric for reconfigurable logic;a behavioral synthesis approach for distributed memory FPGA architectures.
The proceedings contain 86 papers. The topics discussed include: a SAT-based timing driven place and route flow for critical soft ip;lightweight secure processor prototype on FPGA;an application-specific field-program...
ISBN:
(纸本)9781538685174
The proceedings contain 86 papers. The topics discussed include: a SAT-based timing driven place and route flow for critical soft ip;lightweight secure processor prototype on FPGA;an application-specific field-programmable tree ensemble architecture;facilitating easier access to FPGAs in the heterogeneous cloud ecosystems;a demo of FPGA aggressive voltage downscaling: power and reliability tradeoffs;digital pre-distortion implemented using FPGA;accelerated wire-speed packet capture at 200 Gbps;and vicilogic2.0 online learning and prototyping using pYNQ.
The proceedings contain 98 papers. The topics discussed include: high-speed PCAP configuration scrubbing on Zynq-7000 all programmable SoCs;boosting convergence of timing closure using feature selection in a learning-...
ISBN:
(纸本)9782839918442
The proceedings contain 98 papers. The topics discussed include: high-speed PCAP configuration scrubbing on Zynq-7000 all programmable SoCs;boosting convergence of timing closure using feature selection in a learning-driven approach;liquid: fast placement prototyping through steepest gradient descent movement;TeSHoP : a temperature sensing based hotspot-driven placement technique for FPGAs;search-based synthesis of approximate circuits implemented into FPGAs;fast hierarchical NPN classification;and hardware acceleration of feature detection and description algorithms on low-power embedded platforms.
The proceedings contain 63 papers. The topics discussed include: compiler discovered dynamic scheduling of irregular code in high-level synthesis;challenges using FPGA clusters for distributed CNN training;HashCache: ...
ISBN:
(纸本)9798350341515
The proceedings contain 63 papers. The topics discussed include: compiler discovered dynamic scheduling of irregular code in high-level synthesis;challenges using FPGA clusters for distributed CNN training;HashCache: high-performance state tracking for resilient FPGA-based packet processing;Co-Visu: a video super-resolution accelerator exploiting codec information reuse;exploring highly quantized neural networks for intrusion detection in automotive CAN;Titan 2.0: enabling open-source CAD evaluation with a modern architecture capture;pipeline balancing for integrated mapping in high performance spatial programmable architecture;FPGA-accelerated causal discovery with conditional independence test prioritization;and fpl demo: a learning-based motion artefact detector for heterogeneous platforms.
The proceedings contain 81 papers. The topics discussed include: Eciton: very low-power lstm neural network accelerator for predictive maintenance at the edge;an FPGA-based MobileNet accelerator considering network st...
ISBN:
(纸本)9781665437592
The proceedings contain 81 papers. The topics discussed include: Eciton: very low-power lstm neural network accelerator for predictive maintenance at the edge;an FPGA-based MobileNet accelerator considering network structure characteristics;a customizable domain-specific memory-centric FPGA overlay for machine learning applications;modeling attack resistant arbiter PUF with time-variant obfuscation scheme;end-to-end FPGA-based object detection using pipelined CNN and non-maximum suppression;communication-avoiding micro-architecture to compute Xcorr scores for peptide identification;and performance modeling and FPGA acceleration of homomorphic encrypted convolution.
The proceedings contain 168 papers. The topics discussed include: FPGAs at 65nm and beyond- powerful new FPGAs bring new challenges;rapid system-on-a-programmable-chip development and hardware acceleration of ANSI fun...
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ISBN:
(纸本)142440312X
The proceedings contain 168 papers. The topics discussed include: FPGAs at 65nm and beyond- powerful new FPGAs bring new challenges;rapid system-on-a-programmable-chip development and hardware acceleration of ANSI functions;FPGA architecture design methodology;enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration on XILINK FPGAs;65nm FPGAs,a look under the hood: technology, features, and applications;improved interpolation and system integration for FPGA-based molecular dynamics simulations;high performance scientific computing using FPGAs with IEEE floating point and logarithmic architecture for lattice QCD;placement and timing for FPGAs considering variations;FPGA performance optimization via chipwise placement considering process variations;and architecture exploration and tools for pipelined coarse-grained reconfigurable arrays.
The proceedings contain 137 papers. The topics discussed include: a reconfigurable instruction memory hierarchy for embedded systems;low-cost fully reconfigurable data-path for FPGA-based multimedia processor;low-cost...
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ISBN:
(纸本)0780393627
The proceedings contain 137 papers. The topics discussed include: a reconfigurable instruction memory hierarchy for embedded systems;low-cost fully reconfigurable data-path for FPGA-based multimedia processor;low-cost fully reconfigurable data-path for FPGA-based multimedia processor;FPGA PLB evaluation using Quantified Boolean Satisfiability;FELIX: Using rewriting-logic for generating functionally equivalent implementations;high-speed and memory efficient TCP stream scanning using FPGA;mutable codesign for embedded protocol processing;exploiting pipelining to tolerate wire delays in a programmable-reconfigurable processor;applying the Small-World Network to routing structure of FPGAS;MILP-based placement and routing for dataflow architecture;using DSP blocks for ROM replacement: A novel synthesis flow;an FPGA solver for WSAT algorithms;and an efficient and scalable architecture for neural networks with backpropagation learning.
The proceedings contain 7 papers. The topics discussed include: automated generation of reconfigurable systems-on-chip by interactive code transformations for high-level synthesis;a compute model for generating high p...
ISBN:
(纸本)9783800742660
The proceedings contain 7 papers. The topics discussed include: automated generation of reconfigurable systems-on-chip by interactive code transformations for high-level synthesis;a compute model for generating high performance computing SoCs on hybrid systems with FPGAs;an open ecosystem for software programmers to compute on FPGAs;transparent live code offloading on FPGA;an interactive environment for mapping computational structures to FPGAs;and automated inference of SoC configuration through firmware source code analysis.
The proceedings contain 131 papers. The topics discussed include: customizable domain-specific computing;in search of agile hardware;the evolution of architecture exploration of programmable devices;MUCCRA-cube: a 3D ...
ISBN:
(纸本)9781424438921
The proceedings contain 131 papers. The topics discussed include: customizable domain-specific computing;in search of agile hardware;the evolution of architecture exploration of programmable devices;MUCCRA-cube: a 3D dynamically reconfigurable processor with inductive-coupling link;fast critical sections via thread scheduling for FPGA-based multithreaded processors;a biophysically accurate floating point somatic neuroprocessor;compiler assisted runtime task scheduling on a reconfigurable computer;generating high-performance custom floating-point pipelines;exploring reconfigurable architectures for explicit finite difference option pricing models;towards a viable out-of-order soft core: copy-free, checkpointed register renaming;a runtime relocation based workflow for self dynamic reconfigurable systems design;improving logic density through synthesis-inspired architecture;and replace: an incremental placement algorithm for field-programmable gate arrays.
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