The proceedings contain 146 papers. The special focus in this conference is on Communications applications, High Level Design Tools, Reconfigurable Architectures, Cryptographic applications, Place and Route Tools. The...
ISBN:
(纸本)3540408223
The proceedings contain 146 papers. The special focus in this conference is on Communications applications, High Level Design Tools, Reconfigurable Architectures, Cryptographic applications, Place and Route Tools. The topics include: Reconfigurable circuits using hybrid hall effect devices;symbol timing synchronization in FPGA-based software radios;an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix;inter-processor connection reconfiguration based on dynamic look-ahead control of multiple crossbar switches;FPGA implementations of the RC6 block cipher;orchestrating routing structures to maximize routability;virtualizing hardware with multi-context reconfigurable arrays;a dynamically adaptive switching fabric on a multicontext reconfigurable device;reducing the configuration loading time of a coarse grain multicontext reconfigurable device;design strategies and modified descriptions to optimize cipher FPGA implementations;using partial reconfiguration in cryptographic applications;an implementation comparison of an IDEA encryption cryptosystem on two general-purpose reconfigurable computers;low power coarse-grained reconfigurable instruction set processor;encoded-low swing technique for ultra low power interconnect;building run-time reconfigurable systems from tiles;exploiting redundancy to speedup reconfiguration of an FPGA;efficient modular-pipelined AES implementation in counter mode on ALTERA FPGA;an FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm;branch optimisation techniques for hardware compilation;a model for hardware realization of kernel loops;globally asynchronous locally synchronous FPGA architectures and synthesizing on a reconfigurable chip an autonomous robot image processing system.
The following topics are dealt with: fieldprogrammablelogic; design tools and compilers; multicore systems; high performance computing; run-time support; placement and routing; biology applications; power; communica...
The following topics are dealt with: fieldprogrammablelogic; design tools and compilers; multicore systems; high performance computing; run-time support; placement and routing; biology applications; power; communication and security; architecture; image and video processing; and network on chip.
The proceedings contain 74 papers. The special focus in this conference is on Invited Keynote 1 and Architectural Frameworks. The topics include: Technology trends and adaptive computing;prototyping framework for reco...
ISBN:
(纸本)3540424997
The proceedings contain 74 papers. The special focus in this conference is on Invited Keynote 1 and Architectural Frameworks. The topics include: Technology trends and adaptive computing;prototyping framework for reconfigurable processors;an emulator for exploring RaPiD configurable computing architectures;a new placement method for direct mapping into LUT-based FPGAs;fGREP - fast generic routing demand estimation for placed FPGA circuits;macrocell architectures for product term embedded memory arrays;gigahertz reconfigurable computing using SiGe HBT BiCMOS FPGAs;memory synthesis for FPGA-based reconfigurable computers;implementing a hidden markov model speech recognition system in programmablelogic;implementation of (normalised ) RLS lattice on virtex;accelerating matrix product on reconfigurable hardware for signal processing;static profile-driven compilation for FPGAs;synthesizing RTL hardware from java byte codes;from behavioral specification to multi-FPGA-prototype;secure configuration of fieldprogrammable gate arrays;single-chip FPGA implementation of the advanced encryption standard algorithm;jbits™ implementations of the advanced encryption standard (rijndael );task-parallel programming of reconfigurable systems;chip-based reconfigurable task management;configuration caching and swapping;multiple stereo matching using an extended architecture;implementation of a NURBS to bézier conversor with constant latency;reconfigurable frame-grabber for real-time automated visual inspection (RT-AVI ) systems;processing models for the next generation network;tightly integrated placement and routing for FPGAs;a tool for the simultaneous placement and detailed routing of gate-arrays;reconfigurable router modules using network protocol wrappers;development of a design framework for platform-independent networked reconfiguration of software and hardware and the molen ρμ-coded processor.
The expansion of the FPGA into complex market sectors imposes new demands on the security model of the devices. This demonstration shows off a series of tools developed to decode and scan the contents of a bitstream f...
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ISBN:
(纸本)9781665473903
The expansion of the FPGA into complex market sectors imposes new demands on the security model of the devices. This demonstration shows off a series of tools developed to decode and scan the contents of a bitstream for malicious designs.
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