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检索条件"任意字段=2007 International Conference on Field Programmable Logic and Applications, FPL"

共 1861 条记录，以下是41-50 订阅

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Post-LUT-Mapping Implementation of General logic on Carry Chains Via a MIG-Based Circuit Representation 31

Post-LUT-Mapping Implementation of General Logic on Carry Ch...

引用

31st international conference on field-programmable logic and applications (fpl)

作者： Kim, Jin Hee Anderson, Jason Univ Toronto Toronto ON Canada

ISBN: (纸本)9781665437592

Carry chains on FPGAs have traditionally been only used for fast binary arithmetic operations. In this paper, we propose using the carry chain to implement general logic as a means of reducing the critical path delay and raising performance. To achieve this, we use a Majority-Inverter Graph (MIG) to represent the application during technology mapping, since carry functionality directly maps to the majority logic function. This aligns the subject graph of technology mapping with the capabilities of the carry chain. We first map an application to LUTs, then determine a chain of critical LUTs containing paths of majority "gates" that we deem beneficial for mapping onto the carry chain. We place such paths onto the carry chains, with the remaining logic in LUTs. In an experimental study using a suite of benchmarks, we observe that the proposed approach yields a post-place-and-route critical path delay that is superior to using delay-optimized mapping, yet without the significant area penalty. With carry-chain optimizations, area-delay product is improved by 9% vs. baseline LUT mappings.

关键词： Benchmark testing logic functions Table lookup Delays Optimization field programmable gate arrays Arithmetic

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MELODI: An Online Platform for Mass Education of Digital Design - HDL to Remote FPGA 31

MELODI: An Online Platform for Mass Education of Digital Des...

引用

31st international conference on field-programmable logic and applications (fpl)

作者： Bauer, Friedrich Braun, Felix Hauer, Daniel Jantsch, Axel Kobelrausch, Markus D. Mosbeck, Martin TaheriNejad, Nima Vogt, Philipp-Sebastian TU Wien Inst Comp Technol Vienna Austria

ISBN: (纸本)9781665437592

Learning and teaching digital hardware design involves significant efforts on both sides, teachers and students. Hardware Description Languages (HDLs) simplify the design process, where the created designs can be tested either in simulators or using real hardware. For the latter, field programmable Gate Arrays (FPGAs) play a crucial role in facilitating and speeding up the prototyping process. Mass E-Learning of design, test, and prototyping Digital hardware (MELODI) is developed for scalable teaching of HDL to a large number of students. The primary goals are to a) minimize the requirements for students and b) reduce the resources required at the university. MELODI provides a complete HDL workflow, including real remote hardware prototyping on FPGAs without the need for any tool at the students’ side.

关键词： Electronic learning Education Tools logic gates Hardware Hardware design languages field programmable gate arrays

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Design For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core Architectures 31

Design For Agility: A Modular Reconfigurable Platform for He...

引用

31st international conference on field-programmable logic and applications (fpl)

作者： Kamaleldin, Ahmed Goehringer, Diana Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany

ISBN: (纸本)9781665437592

Reconfigurable many-core computing platforms are gaining increasing attention for cloud and edge computing because of their high degree of scalability as well as flexibility. Heterogeneous many-core architectures provide more computing capabilities for domain-specific and general-purpose applications. However, bringing heterogeneous and custom computing elements together increases on-chip communication and run-time management complexities. This leads to growing design time and development cost, in addition to lack of platform re-usability. The scope of this PhD work is the design of a modifiable and modular hardware platform that provides a high degree of agility to change types or specifications of computing elements at design and run-time to achieve the best performance for different application demands using the same platform components. Different acceleration strategies and memory hierarchies are supported. In this paper, the proposed platform, preliminary results, and evaluation are presented targeting FPGAs. Finally, planned and future works are highlighted.

关键词： Reconfigurable computing many-core architecture field programmable gate arrays (FPGA)

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Minimal Overhead Optical Time-Domain Reflectometer Via I/O Integrated Data Converter Enabled by field programmable Voltage Offset 31

Minimal Overhead Optical Time-Domain Reflectometer Via I/O I...

引用

31st international conference on field-programmable logic and applications (fpl)

作者： Mauldin, Thomas Xu, Zhenyu Wei, Tao Univ Rhode Isl Elect Comp & Biomed Engn Kingston RI 02881 USA

ISBN: (纸本)9781665437592

As optical reflectometers become more mature technologies, their capabilities are reaching new highs;however, modern designs not only push the performance of the systems, but also the cost and form-factor. As a result, many of the proposed high-performance devices have not been widely adopted for industry use. This paper takes a step back and not only demonstrates a high-performance optical time-domain reflectometer but does so using components that are already in existence in a communication network, such as transmitter optical sub-assembly (TOSA), receiver optical sub-assembly (ROSA), field programmable gate arrays (FPGA) and system-on-chip (SoC) architecture. Thus, it is possible for this design to be integrated in any fiber-optic transceiver in the future. This is enabled by the field programmable voltage offset (FPVO) calibration capabilities of an internal input buffer, typically used to compensate for process variations, which can be used to achieve a reconfigurable and chip-integrated small signal data converter. Using this data converter in an optical time-domain reflectometer, a minimal overhead design is realized with an optical power sensitivity of -52dBm and dynamic range of 23.5dB.

关键词： Data converter field-programmable optical time-domain reflectometry reconfigurable

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Load Balance -Centric Distributed ParallelRouting for Large -Scale FPGAs 31

Load Balance -Centric Distributed ParallelRouting for Large ...

引用

31st international conference on field-programmable logic and applications (fpl)

作者： Shen, Minghua Xiao, Nong Sun Yat Sen Univ Sch Comp Sci & Engn Guangzhou Peoples R China

ISBN: (纸本)9781665437592

Routing is one of the most time-consuming stages in the FPGA design flow. Parallelization can accelerate the routing process but suffering from load imbalance, further resulting in a low scalahility. In this paper, we propose a load balance -centric parallel router in a distributed computing environment. First, we explore regular and irregular region partitioning so that routing tasks arc assigned to different cores for static load balance before parallel routing. Second, we explore message propagation and task migration between underloaded and overloaded cores so that load balance can be dynamically maintained at parallel routing runtime. Finally, we demonstrate the effectiveness of the parallel router using large-scale Titan designs. Experimental results show that our parallel router achieves about 17x speedup on average using 32 cores, compared with VTR 8 router.

关键词： Degradation Runtime Scalability Routing Task analysis Distributed computing field programmable gate arrays

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Distributed Recommendation Inference on FPGA Clusters 31

Distributed Recommendation Inference on FPGA Clusters

引用

31st international conference on field-programmable logic and applications (fpl)

作者： Zhu, Yu He, Zhenhao Jiang, Wenqi Zeng, Kai Zhou, Jingren Alonso, Gustavo Swiss Fed Inst Technol Syst Grp Zurich Switzerland Alibaba Grp Hangzhou Peoples R China

ISBN: (纸本)9781665437592

Deep neural networks are widely used in personalized recommendation systems. Such models involve two major components: the memory-bound embedding layer and the computation-bound fully-connected layers. Existing solutions are either slow on both stages or only optimize one of them. To implement recommendation inference efficiently in the context of a real deployment, we design and implement an FPGA cluster optimizing the performance of both stages. To remove the memory bottleneck, we take advantage of the High-Bandwidth Memory (HBM) available on the latest FPGAs for highly concurrent embedding table lookups. To match the required DNN computation throughput, we partition the workload across multiple FPGAs interconnected via a 100 Gbps TCP/IP network. Compared to an optimized CPU baseline (16 vCPU, AVX2-enabled) and a one-node FPGA implementation, our system (four-node version) achieves 28.95x and 7.68x speedup in terms of throughput respectively. The proposed system also guarantees a latency of tens of microseconds per single inference, significantly better than CPU and GPU-based systems which take at least milliseconds.

关键词： Deep learning Computational modeling TCPIP Throughput Table lookup field programmable gate arrays

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DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern field programmable Gate Arrays 31

DeepFire: Acceleration of Convolutional Spiking Neural Netwo...

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31st international conference on field-programmable logic and applications (fpl)

作者： Aung, Myat Thu Linn Qu, Chuping Yang, Liwei Luo, Tao Goh, Rick Siow Mong Wong, Weng-Fai Agcy Sci Technol & Res Inst High Performance Comp Singapore Singapore Natl Univ Singapore Dept Comp Sci Singapore Singapore

ISBN: (纸本)9781665437592

Spiking neural networks (SNN) with their 'integrate and fire' (I&F) neurons replace the hardware-intensive multiply-accumulate (MAC) operations in convolutional neural networks (CNN) with accumulate operations not only making it easy to implement on FPGAs but also opening up the opportunities for energy-efficient hardware acceleration. In this paper, we propose DeepFire the high-performance RTL IP - for accelerating convolutional SNN inference. The IP exploits various resources available on modern FPGAs, and it outperforms existing SNN implementations by more than 10x in terms of both frame per second (FPS) and performance per watt (FPS/Watt). Our design achieves up to 40.1kFPS and 28.3kFPS on MNIST and CIFAR-10/SVHN datasets with 99.14% and 81.8%/93.1% accuracies respectively. IP was evaluated with 7-series and Ultrascale+ FPGAs from Xilinx achieving Fmax of 375MHz and 500MHz respectively.

关键词： Neuromorphic Computing Integrate and Fire Acceleration Hardware FPGA

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SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs 31

SyncNN: Evaluating and Accelerating Spiking Neural Networks ...

引用

31st international conference on field-programmable logic and applications (fpl)

作者： Panchapakesan, Sathish Fang, Zhenman Li, Jian Simon Fraser Univ Sch Engn Sci Burnaby BC Canada Futurewei Technol Inc Santa Clara CA USA

ISBN: (纸本)9781665437592

In this paper, we propose a novel synchronous approach for rate encoding based Spiking Neural Networks (SNNs), which is more hardware friendly than conventional asynchronous approaches. We also design and implement the SyncNN framework to accelerate SNNs on Xilinx ARM-FPGA SoCs in a synchronous fashion. To improve the computation and memory access efficiency, we first quantize the network weights to 16-bit, 8-bit, and 4-bit fixed-point values with the SNN friendly quantization technique. For the encoded neurons that have dynamic and irregular access patterns, we design parameterized compute engines to accelerate their performance on the FPGA, where we explore various parallelization strategies and memory access optimizations. Our experimental results on multiple Xilinx ARM-FPGA SoC boards demonstrate that our SyncNN is scalable to run multiple networks, such as LeNet, Network in Network, and VGG, on various datasets such as MNIST, SVHN, and CIFAR-10. SyncNN not only achieves competitive accuracy (99.6%) but also achieves state-of-the-art performance (13,086 frames per second) for the MNIST dataset.

关键词： Quantization (signal) Neurons Memory management Hardware Encoding Computational efficiency field programmable gate arrays

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A High-Performance Routing Engine for Large-Scale FPGAs

A High-Performance Routing Engine for Large-Scale FPGAs

引用

international conference on field programmable logic and applications

作者： Timothy Martin Dani Maarouf Gary Grewal Shawki Areibi University of Guelph Guelph Ontario Canada

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Routing is the most time-consuming stage in the field programmable Gate Array (FPGA) design workflow. We propose a parallel routing technology, based on the Pathfinder algorithm, that enhances parallelism by dividing the search into two phases: one that tolerates overlaps and one that does not. Additional performance optimizations include an improved cost schedule, pruning the routing-resource graph, and selecting efficient data structures for modern CPUs. Evaluated using both the 2023 MLCAD and 2024 FPGA Routing Contest benchmarks, our router achieves average speedups of $6.2 \times$ and $5.2 \times$ compared to RWRoute and Vivado 2023.2, respectively.

关键词： Schedules Costs Heuristic algorithms Benchmark testing Routing Dynamic scheduling Timing field programmable gate arrays Optimization Engines

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A Better Kyber Butterfly for FPGAs

A Better Kyber Butterfly for FPGAs

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international conference on field programmable logic and applications

作者： Jonas Bertels Quinten Norga Ingrid Verbauwhede COSIC KU Leuven Leuven Belgium

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Kyber was selected by NIST as a Post-Quantum Cryptography Key Encapsulation Mechanism standard. This means that the industry now needs to transition and adopt these new standards. One of the most demanding operations in Kyber is the modular arithmetic, making it a suitable target for optimization. This work offers a novel modular reduction design with the lowest area on Xilinx FPGA platforms. This novel design, through K-reduction and LUT-based reduction, utilizes 49 LUTs and 1 DSP as opposed to Xing and Li’s [XL21] 2021 CHES design requiring 90 LUTs and 1 DSP for one modular multiplication. Our design is the smallest modular multiplier reported as of today.

关键词： Industries Costs Merging NIST Table lookup logic field programmable gate arrays Standards Optimization Arithmetic

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