This paper introduces hthreads, a unifying programming model for specifying application threads running within a hybrid computer processing unit (CPU)/field-programmable gate-array (FPGA) system. Presently accepted hy...
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This paper introduces hthreads, a unifying programming model for specifying application threads running within a hybrid computer processing unit (CPU)/field-programmable gate-array (FPGA) system. Presently accepted hybrid CPU/FPGA computational models-and access to these computational models via high level languages-focus on programming language extensions to increase accessibility and portability. However, this paper argues that new high-level programming models built on common software abstractions better address these goals. The hthreads system, in general, is unique within the reconfigurable computing community as it includes operating system and middleware layer abstractions that extend across the CPU/FPGA boundary. This enables all platform components to be abstracted into a unified multiprocessor architecture platform. Application programmers can then express their computations using threads specified from a single POSIX threads (pthreads) multithreaded application program and can then compile the threads to either run on the CPU or synthesize them to run within an FPGA. To enable this seamless framework, we have created the hardware thread interface (HWTI) component to provide an abstract, platform-independent compilation target for hardware-resident computations. The HWTI enables the use of standard thread communication and synchronization operations across the software/hardware boundary. Key operating system primitives have been mapped into hardware to provide threads running in both hardware and software uniform access to a set of sub-microsecond, minimal-jitter services. Migrating the operating system into hardware removes the potential bottleneck of routing all system service requests through a central CPU.
Testbench generation is of great importance for function verification of RCA. Traditional testbench generation using pseudo-random method is not very effective;so many other generations have been developed. In this pa...
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ISBN:
(纸本)9781424420636
Testbench generation is of great importance for function verification of RCA. Traditional testbench generation using pseudo-random method is not very effective;so many other generations have been developed. In this paper, genetic algorithm based generation with syntax restriction is introduced at length. The method with syntax restriction not only generates more executable testbenches for reconfigurable media processor but also has high coverage and efficiency than pseudo-random generation method. Two programs using this method and pseudo-random generation are designed respectively, and experiment results comparison are represented at the end of the paper, which shows that genetic algorithm with syntax restriction will benefit testbench generation.
Program and General Chair of CAI-2008 provides a brief survey of each of a hundred papers included into the program of the conference. Being one of the series of biannual conferences, the conference CAI-2008, was orga...
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Program and General Chair of CAI-2008 provides a brief survey of each of a hundred papers included into the program of the conference. Being one of the series of biannual conferences, the conference CAI-2008, was organized and held by the Russian Association for Artificial Intelligence (RAAI) in the city Dubna (Moscow region) from September 28th to October 3d, 2008. The purpose of the present survey is to give a general idea of each paper by a brief exposition of its contents. The full texts of the original papers may be found in the first two volumes of the Proceedings of this conference (Moscow: URSS, 2008).
In the block ciphers, though the operation is quite complex, there are a lot of similar characteristics including arithmetic unit, operation width, parallel data and ordinal implement. It is very suitable for designin...
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ISBN:
(纸本)9780769532875
In the block ciphers, though the operation is quite complex, there are a lot of similar characteristics including arithmetic unit, operation width, parallel data and ordinal implement. It is very suitable for designing ASIP (Application Specific Instruction Set Processor) targeted at block ciphers. In this thesis, a reconfigurable processor architecture is proposed, At the mean time, in order to improve instruction level parallelism. This thesis put forward the instruction bundle structure based on VLIW architecture, which supports word and sub-word parallel processing. As to the design of cipher arithmetic units, we adopt a specific design which is reconfigurable, so as to make the architecture have instruction level reconfigurable function. Besides, In order to solve the bottleneck of storage and access, this thesis adopt clustered technology to design two separated register files to storage data and subkey. Furthermore, this scheme reduces energy and clock cycles. A number of algorithms were implemented successfully on the processor. The prototype is realized using Altera's FPGA. Synthesis, placement and routing of processor have accomplished under 0.18 mu m CMOS technology through Design Complier tool. Compared with other ASIP targeted at block cipher, the results prove that processor can achieve relatively high performance in block cipher algorithms processing.
The proceedings contain 76 papers. The topics discussed include: reconfigurable PDA for the visually impaired using FPGAs;embedded harmonic control for trajectory planning in large environments;flexible architecture f...
ISBN:
(纸本)9780769534749
The proceedings contain 76 papers. The topics discussed include: reconfigurable PDA for the visually impaired using FPGAs;embedded harmonic control for trajectory planning in large environments;flexible architecture for three classes of optical flow extraction algorithms;automatic synthesis of multiprocessor systems from parallel programs under preemptive scheduling;design and implementation of a resource-efficient communication architecture for multiprocessors on FPGAs;automatic instruction-set extensions with the linear complexity spiral search;a real-time embedded system for stereo vision preprocessing using an FPGA;finite precision analysis of the 3GPP standard turbo decoder for fixed- point implementation in FPGA devices;parallel processor for 3D recovery from optical flow;and a reconfigurable platform for frequent pattern mining.
This paper presents a very efficient approach for algorithms developed based on conformal geometric algebra using reconfigurable hardware. We use the inverse kinematics of the arm of a virtual human as an example, but...
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ISBN:
(纸本)9789898111203
This paper presents a very efficient approach for algorithms developed based on conformal geometric algebra using reconfigurable hardware. We use the inverse kinematics of the arm of a virtual human as an example, but we are convinced that this approach can be used in a wide field of computer animation applications. We describe the original algorithm on a very high geometrically intuitive level as well as the resulting optimized algorithm based on symbolic calculations of a computer algebra system. The main focus then is to demonstrate our approach for the hardware implementation of this algorithm leading to a very efficient implementation.
The demands on today's products have become increasingly complex as customers expect enhanced performance across a variety of diverse and changing system operating conditions. reconfigurablesystems are capable of...
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ISBN:
(纸本)9780791848074
The demands on today's products have become increasingly complex as customers expect enhanced performance across a variety of diverse and changing system operating conditions. reconfigurablesystems are capable of undergoing changes in order to meet new objectives, function effectively in varying operating environments, and deliver value in dynamic market conditions. Research in the design of such responsive and changeable systems, however, currently faces impediments in effective and clear discourse due to ambiguity in terminology. Definitions of the terms flexibility and reconfigurability, two related concepts in reconfigurable system design, are explored based on their original lexical meanings and current understanding in design literature. Design techniques that incorporate flexibility both in the design (form) and performance (function) space are presented. Based upon this literature survey, a classification scheme for flexibility is proposed, and its application to reconfigurable system design is explored. This paper also presents recent methodologies for reconfigurable system design and poses important research questions that remain to be investigated.
The proceedings contain 28 papers. The topics discussed include: Picoserver- building a compact energy efficient multiprocessor;challenges in embedded system simulation;towards unified mechanisms for inter-processor c...
ISBN:
(纸本)9781424419852
The proceedings contain 28 papers. The topics discussed include: Picoserver- building a compact energy efficient multiprocessor;challenges in embedded system simulation;towards unified mechanisms for inter-processor communication;a general model of concurrency and its implementation as many-core dynamic RISC processors;a parameterized dataflow language extension for embedded streaming systems;an architecture for the simultaneous execution of hard real-time threads;an adaptive bloom filter cache partitioning scheme for multicore architectures;realizing reconfigurable mesh algorithms on softcore arrays;a light-weight network-on-chip architecture for dynamically reconfigurablesystems;systematic design space exploration for customisable multi-processor architectures;and clustering method for the identification of convex disconnected multiple input multiple output instructions.
The paper describes novel multimedia tools and architectures for hardware/software co-simulation of reconfigurablesystems. The main contributions are provided in the following three areas: 1) multimedia tools making ...
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ISBN:
(纸本)9780769530833
The paper describes novel multimedia tools and architectures for hardware/software co-simulation of reconfigurablesystems. The main contributions are provided in the following three areas: 1) multimedia tools making it possible to manage animated graphical objects for virtual simulation of real world physical objects in the scope of reconfigurable system design;2) a remotely accessible prototyping system, which is very helpful for both solving the problems of hardware design and supporting multimedia systems which can be used in vast varieties of practical applications, the most important Of which are engineering training and education;3) design methodology based on physical circuits and virtual objects. A number of illustrative examples demonstrating capabilities of the proposed approach are presented and discussed.
The paper considers development and application of extremal correlation reconfigurable navigation systems, which feature advanced accuracy, operation speed, and reliability.
ISBN:
(纸本)9785900780801
The paper considers development and application of extremal correlation reconfigurable navigation systems, which feature advanced accuracy, operation speed, and reliability.
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