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检索条件"任意字段=2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008"

共 2738 条记录，以下是21-30 订阅

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Optimizing pipelining in HDL generated automatically from C source codes

Optimizing pipelining in HDL generated automatically from C ...

引用

2008 international conference on engineering of reconfigurable systems and algorithms, ersa 2008

作者： Holland, Wesley Dandass, Yoginder S. Computer Science and Engineering Mississippi State University Starkville MS United States

ISBN: (纸本)1601320647

reconfigurable computing has the potential for providing significant performance increases to a number of computing applications. However, realizing these benefits has traditionally required extensive digital design experience and knowledge of hardware description languages (HDL). While a number of academic and commercial products have focused on translation of highlevel languages (HLL) to HDL, the tools do not create optimized digital designs that are competitive with handcoded solutions for all instances of input HLL code. In this paper, we describe an optimization in the C-to-HDL transformation that automatically reorganizes operations between pipeline stages in order to reduce critical path lengths. This optimization results in significant improvement in design frequency and throughput, especially for algorithms that cannot be pipelined effectively. The effects of this optimization are examined on SHA-1 and Smith-Waterman algorithms. Results show that the automatically generated hardware implementations perform comparably with hand-coded implementations.

关键词： Computer hardware description languages

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Multicore devices: A new generation of reconfigurable architectures

Multicore devices: A new generation of reconfigurable archit...

引用

2008 international conference on engineering of reconfigurable systems and algorithms, ersa 2008

作者： Guccione, Steven A. Cmpware Inc. Austin TX United States

ISBN: (纸本)1601320647

For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. reconfigurable computing systems have demonstrated the low cost and flexibility of a software solution combined with the high performance of fixed hardware. For a variety of practical reasons, much of the work in this area focused on commercial FPGA devices as the underlying hardware platform. Recently, several new designs have diverged from the bit-level, circuit-oriented architectures of FPGAs and produced a variety of architectures more suitable for computation and high level language programming. These new highly parallel architectures contain a relatively large number of programmable cores, each approaching the complexity of a traditional microprocessor. Today such devices can be found in popular consumer electronics including game consoles and desktop PC graphics controllers as well as a new generation of supercomputers. These new devices, often described using the generic term 'multicore' represent the latest phase in the evolution of reconfigurable systems. Like earlier reconfigurable systems they promise very high performance at relatively low power with high levels of programmability. These new systems also feature software development tools geared more toward traditional high level language programming than the hardware design orientation found in earlier generations of reconfigurable systems.

关键词： reconfigurable architectures

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Multiparadigm computing for space-based synthetic aperture radar

Multiparadigm computing for space-based synthetic aperture r...

引用

2008 international conference on engineering of reconfigurable systems and algorithms, ersa 2008

作者： Jacobs, Adam Cieslewski, Grzegorz Reardon, Casey George, Alan D. Research Laboratory United States Department of Electrical and Computer Engineering University of Florida United States

ISBN: (纸本)1601320647

Projected computational requirements for future space missions are outpacing technologies and trends in conventional embedded microprocessors. In order to meet the necessary levels of performance, new computing technologies are of increasing interest for space systems, such as reconfigurable devices and vector processing extensions. These new technologies can also be used in tandem with conventional generalpurpose processors in the form of multiparadigm computing. By using FPGA resources and AltiVec extensions, as well as MPI extensions for multiprocessor support, we explore possible hardware/software designs for a synthetic aperture radar application. Design of key components of the SAR application including range compression and azimuth compression will be discussed, and hardware/software performance tradeoffs analyzed. The performance of these key components will be measured individually, as well as in the context of the entire application. Fault-tolerant versions of range and azimuth compression algorithms are proposed and their performance overhead is evaluated. Our analysis compares several possible multiparadigm systems, achieving up to 18 speedup while also adding fault tolerance to a pre-existing SAR application.

关键词： Synthetic aperture radar

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XF-BOARD: A prototyping platform for reconfigurable hardware operating systems

XF-BOARD: A prototyping platform for reconfigurable hardware...

引用

international conference on engineering of reconfigurable systems and algorithms (ersa 04)

作者： Walder, H Nobs, S Platzner, M Swiss Fed Inst Technol Comp Engn & Networks Lab TIK Zurich Switzerland

ISBN: (纸本)1932415424

We present the XF-BOARD, a prototyping platform for reconfigurable hardware operating system research. The platform is based on two tightly coupled FPGAs. The first (C-FPGA) implements a soft CPU core that controls the overall system;the second (R-FPGA) is used as dynamically reconfigurable hardware resource. Furthermore, a rich set of I/O and memory devices are available for implementing multimedia and networking applications.

关键词： Computer operating systems

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Evaluation of MuCCRA-D: A dynamically reconfigurable processor with directly interconnected PEs

Evaluation of MuCCRA-D: A dynamically reconfigurable process...

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2008 international conference on engineering of reconfigurable systems and algorithms, ersa 2008

作者： Kato, Masaru Hasegawa, Yohei Amano, Hideharu Department School of Science and Technology Keio University 3-14-1 Hiyoshi Yokohama 223-8522 Japan

ISBN: (纸本)1601320647

Coarse-grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Chips (SoCs). Interconnection in these architectures is one of the important factors to be evaluated. MuCCRA-1, the first prototype of MuCCRA(Multi-Core Configurable reconfigurable Architecture) project, uses a typical island-style interconnection in its PE array. Although the island-style interconnection is flexible, the large delay time caused by passing multiple switches and long wires often degrades its clock frequency. In this paper, MuCCRA-D, a dynamically reconfigurable processor which uses direct interconnection between neighboring PEs, is designed and evaluated. The evaluation results show that the required semiconductor area for MuCCRA-D is 12% smaller than that of MuCCRA-1 by reducing wiring resource in the interconnection. Since higher clock frequency can be used, DCT, α-Blending, Bubble-Sort and SHA-1 implemented on the MuCCRA-D are 3.84 times faster than MuCCRA-1 at maximum.

关键词： reconfigurable architectures

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On FPGA design with self-checking and fault tolerance capability

On FPGA design with self-checking and fault tolerance capabi...

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2008 international conference on engineering of reconfigurable systems and algorithms, ersa 2008

作者： Lala, P. Department of Electrical Engineering Texas A and M University Texarkana TX United States

ISBN: (纸本)1601320647

This paper discusses the work done by the author and his coworkers in the area of self-checking and fault tolerant FPGA design. It also proposes an FPGA architecture that is composed of functional cells with built in error correction capability. A functional cell in the proposed architecture can be used to implement logic functions as well as to route signals to other functional cells. It is composed of three units: a logic block, a faulttolerant address generator and a director unit. The logic block uses a look-up table to implement logic functions. The fault-tolerant address generator corrects any single bit error in the incoming data to the functional cell. The director block can transmit output data from the logic block to another functional cell located at its South, North, East or West, or to cells in all four directions.

关键词： Cells

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A new tact in reconfigurable computing research

A new tact in reconfigurable computing research

引用

2008 international conference on engineering of reconfigurable systems and algorithms, ersa 2008

作者： Watson, J. Kelem, S. Box, B. Hassoun, J. Wasson, S. Plunkett, R. Phillips, C. Element CXI Milpitas CA United States

ISBN: (纸本)1601320647

For the most part, reconfigurable architectures have been based on existing IC architectures or combinations of them. To date, they have lukewarm success at best. A fundamentally different thought process is needed to unleash the value of adapting hardware to the problem at hand. One that delivers on the promise of super-computer performance on battery power at consumer price points to replace ASIC, SOC, FPGA and multi-processor solutions. Every engineer understands the definition of work as W=F*D Cos Θ. This is the definition used in physics. But, when asked what the definition of work is in electronic circuits you get a blank stare followed by, "it must have something to do with energy, MHz, bus width, etc." In other words, you do not receive a credible answer. This paper explores a few research concepts and opportunities in regards to a definition of work in electronics and its implication in the definition of reconfigurable architectures.

关键词： reconfigurable architectures

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A framework to improve IP portability on reconfigurable computers

A framework to improve IP portability on reconfigurable comp...

引用

2008 international conference on engineering of reconfigurable systems and algorithms, ersa 2008

作者： Huang, Miaoqing Gonzalez, Ivan Lopez-Buedo, Sergio El-Ghazawi, Tarek Department of Electrical and Computer Engineering George Washington University United States

ISBN: (纸本)1601320647

This paper presents a framework that improves the portability and ease-of-use issues of current reconfigurable Computers (RCs). These two drawbacks should be solved in order for RC to become a mainstream solution. Portability across platforms is difficult to achieve because RC systems have diverse hardware architectures and services. This lack of portability hinders reuse, and thus, ease-of-use. The framework proposed in this work is able to hide the architectural details of the systems, simplify the IP integration, and provide the portability across different RC platforms. User specifies IP requirements such as memory configuration, sequential or random access to the memory, or I/O registers using a graphical-user-interface (GUI) tool, which generates a hardware interface specification for the IP and the logic necessary to target the selected platform. The hardware interface remains the same regardless the targeted architecture. In addition, the tool generates a software library that includes services such as bitstream management and data exchange between microprocessor and IP. This framework has been demonstrated on two representative RCs: Cray XD1 and SGI RASC RC100.

关键词： Field programmable gate arrays (FPGA)

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Physical resource binding for a coarse grain reconfigurable array

Physical resource binding for a coarse grain reconfigurable ...

引用

international conference on engineering of reconfigurable systems and algorithms (ersa 04)

作者： Ma, F Knight, J Plett, C Carleton Univ Dept Elect Ottawa ON K1S 5B6 Canada

ISBN: (纸本)1932415424

One of the challenges of designing for coarse grain reconfigurable arrays is the need for mature tools. This is especially important because of the heterogeneity of the larger, more predefined (and hence more specialized) array elements. This work describes the use of a genetic algorithm (GA) to automate the physical binding phase of kernel design. We identify the generalizable features of an example platform and discuss ways to harness the binding problem to a GA search engine.

关键词： reconfigurable architectures genetic algorithms field programmable gate arrays physical resource binding

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Traveltrek: Effortless Travel Crafting and Management

Traveltrek: Effortless Travel Crafting and Management

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Intelligent Control, Computing and Communications (IC3), international conference on

作者： Himanshu Pushpendra Singh Vinai Kumar Singh Department of Computer Science and Engineering SRM Institute of Science and Technology Delhi-NCR Campus Ghaziabad India Department of Applied Science and Humanities GL BAJAJ Group of Institutions Mathura India

ISBN: (数字)9798331527495

ISBN: (纸本)9798331527501

Today's rapidly changing world has led travelers to seek customized experiences that align with their individual preferences and interests. With the continuous evolution of the digital realm, the expectations of users interacting with online platforms for travel planning and reservations are also evolving. To cater to the demand for personalized recommendations and enhance the user experience, we propose the incorporation of a Content-Based Filtering algorithm into our tour website. This algorithm, in conjunction with a recommender system for Travel and tourism management, enables users to book tours nationwide through a single dynamic website that provides comprehensive information on various destinations and tour specifics. Developed with PHP as the front end and Microsoft SQL Server 2008 as the back end, the website is compatible with all browsers. Programming languages such as HTML, CSS, Bootstrap, and PHP were utilized in its creation. Administrators have the capability to add tour packages from selected travel agents and hotels by establishing a tour page. Subsequently, users can register and reserve each package, with confirmation managed by the admin in the booking management section. Users can easily view their confirmations in the “My Booking” page, making this platform user-friendly for all travelers seeking seamless bookings and detailed information. Furthermore, alongside implementing a Content-Based Filtering algorithm for personalized tour recommendations, we aim to promote the availability of accommo-dations in local rural areas. This endeavor not only presents travelers with cost-effective lodging choices but also contributes to the economic growth of the communities they visit.

关键词： Heuristic algorithms System performance Transportation Filtering algorithms User experience Planning Registers Servers Recommender systems Testing

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