A research team at the University of South Carolina has been conducting an extensive test of a commercial reconfigurable machine to determine its usability as a "computer" in the ordinary sense of the term. ...
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ISBN:
(纸本)1932415424
A research team at the University of South Carolina has been conducting an extensive test of a commercial reconfigurable machine to determine its usability as a "computer" in the ordinary sense of the term. Implementations of a number of computationally intensive applications have been attempted with varying degrees of success. The experiences with this machine are related here in order to present an analysis of this particular machine at this particular time as well as to posit fundamental requirements that a reconfigurable machine must meet in order to be considered a generally-usable programmable computer for augmenting the solution of computationally difficult problems.
Computational biologists are turning to reconfigurable computing to solve bioinformatics grand challenges such as genome sequence analysis. While reconfigurable, computing hardware has been available for many years, t...
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ISBN:
(纸本)1932415424
Computational biologists are turning to reconfigurable computing to solve bioinformatics grand challenges such as genome sequence analysis. While reconfigurable, computing hardware has been available for many years, the tools necessary to apply the technology to large-scale computing have not been available. Starbridge introduces a solution in the form of the patented Hypercomputer, a reconfigurable computing system, and patent-pending Viva;an FPGA development environment Using Viva;Starbridge implemented a massively-parallel Smith-Waterman algorithm on a Hypercomputer The result was a complete comparison of the X and Y chromosome that took five days to process.
Light Detection and Ranging (LIDAR) plays an important role in remote sensing because of its ability to provide high-resolution measurements of 3D structure. For time-sensitive airborne missions, fast onboard processi...
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ISBN:
(纸本)1601320647
Light Detection and Ranging (LIDAR) plays an important role in remote sensing because of its ability to provide high-resolution measurements of 3D structure. For time-sensitive airborne missions, fast onboard processing of LIDAR data is desired and yet difficult to achieve with traditional embedded CPU solutions due to the computational requirements. FPGAs have the potential to speed up processing by employing multi-level parallelism, but their use in LIDAR processing has typically been limited to data capture due to the difficulties associated with efficiently migrating LIDAR processing algorithms to FPGAs. We demonstrate two equivalent FPGA designs for coordinate calculation of LIDAR data written using different languages (VHDL and MATLAB-based AccelDSP), comparing their performance and productivity. For the VHDL design, a ∼14 speedup is obtained over an Opteron processor on a Cray XD1 system. In addition, a recently proposed performance prediction methodology is employed, and the accuracy of its pre-implementation predictions is analyzed.
This paper proposes the design of a tool that automates the generation of the target architecture onto which reconfigurable logic blocks are mapped. The target architecture is hierarchical in nature and includes both ...
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ISBN:
(纸本)1932415424
This paper proposes the design of a tool that automates the generation of the target architecture onto which reconfigurable logic blocks are mapped. The target architecture is hierarchical in nature and includes both the number and complexity of the interconnect switches at each level. The architecture is generated based on our proposed vector space model for representing interconnections between reconfigurable blocks. The automation is based on our modified version of constrained agglomerative hierarchical clustering that has been proven as the best hierarchical clustering approach in the field of data mining. The proposed architecture optimizes both transient and static power while meeting timing constraints.
This paper proposes a reconfigurable parallel architecture for space-borne on-board processing that combines the advantages of powerful computational resources with a straightforward software development. This approac...
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ISBN:
(纸本)1932415424
This paper proposes a reconfigurable parallel architecture for space-borne on-board processing that combines the advantages of powerful computational resources with a straightforward software development. This approach introduces the concept of software payloads that enable the users the direct transfer of their ground-based applications towards space and thus the circumvention of the usual downlink bottleneck. The main emphasis is on the processing model and the software development aspect. The advantages in the proposed system are highlighted by a series of demonstration applications. A trade-off analysis of these suggested processing tasks with respect to a ground-based solution concludes the investigation.
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarchies. Mapping applications to these com...
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ISBN:
(纸本)1932415424
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarchies. Mapping applications to these complex systems requires a representation that allows both hardware and software synthesis. Additionally, this representation must enable optimizations that exploit fine and coarse grained parallelism in order to effectively utilize the performance of the underlying reconfigurable architecture. Our work explores a representation based on the program dependence graph (PDG) incorporated with the static single-assignment (SSA) for synthesis to high performance reconfigurable devices. The PDG effectively describes control dependencies, while SSA yields precise data dependencies. When used together these two representations provide a powerful, synthesizable form that exploits both fine and coarse grained parallelism. Compared to other commonly used representations for reconfigurablesystems, the PDG + SSA form creates faster execution time, while using similar area.
This paper describes the design and implementation of a portable face recognition system using reconfigurable hardware. The hardware platform is named iPACE-V2 (Image Processing Adaptive Computing Engine) which is a p...
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ISBN:
(纸本)1932415424
This paper describes the design and implementation of a portable face recognition system using reconfigurable hardware. The hardware platform is named iPACE-V2 (Image Processing Adaptive Computing Engine) which is a portable, reconfigurable hardware platform, designed for real time, in-field image processing applications. We have implemented the Eigenfaces approach for face recognition on this system. We have used the FERET database of facial images [1] for testing purposes. We implemented the face recognition algorithm with various numbers of functional units to study the speedup effects. Our results show significant improvement in the execution time as compared to a desktop system running a similar application.
This paper discusses the implementation of multi-standard communication systems in dynamically reconfigurable heterogeneous hardware. An overview of a wireless LAN communication system, namely HiperLAN/2, and a Blueto...
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ISBN:
(纸本)193241505X
This paper discusses the implementation of multi-standard communication systems in dynamically reconfigurable heterogeneous hardware. An overview of a wireless LAN communication system, namely HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in a reconfigurable architecture are discussed. Suggestions for future activities in the Adaptive Wireless Networking project are also given.
This paper presents an approach for designing reconfigurable processors to improve the performance of software compiled for static processors. By reconfiguring between different application specific cores of the same ...
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ISBN:
(纸本)1932415424
This paper presents an approach for designing reconfigurable processors to improve the performance of software compiled for static processors. By reconfiguring between different application specific cores of the same programming model, a soft processor core can be redesigned with improved performance without having to rewrite software for the processor, an inherent problem in other reconfigurablesystems. This project involved a proof-of-concept implementation.
Mobile wireless terminals tend to become multi-mode wireless communication devices. Furthermore, these devices become adaptive. Heterogeneous reconfigurable hardware provides the flexibility, performance and efficienc...
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ISBN:
(纸本)9781932415742
Mobile wireless terminals tend to become multi-mode wireless communication devices. Furthermore, these devices become adaptive. Heterogeneous reconfigurable hardware provides the flexibility, performance and efficiency to enable the implementation of these devices. The implementation of a WCDMA and an OFDM receiver in the same coarse-grained reconfigurable Montium processor is discussed.
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