The proceedings contain 30 papers. The topics discussed include: reliability-aware multi-vth domain digital design assessment;replication-based deterministic testing of 2-dimensional arrays with highly interrelated ce...
ISBN:
(纸本)9781538657546
The proceedings contain 30 papers. The topics discussed include: reliability-aware multi-vth domain digital design assessment;replication-based deterministic testing of 2-dimensional arrays with highly interrelated cells;contribution to automated generating of system power-management specification;a rare event based yield estimation methodology for analog circuits;two-stage bulk-driven variable gain amplifier for low-voltage applications;heuristic for page-based incremental reprogramming of wireless sensor nodes;tuning stochastic space compaction to faster-than-at-speed test;constraint-based pattern retargeting for reducing localized power activity during testing;and an integrated phase shifting frequency synthesizer for active electronically scanned arrays.
Neural networks with quantized activation functions cannot adapt the quantization at the input of their first layer. Preprocessing is therefore required to adapt the range of input data to the quantization range. Such...
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ISBN:
(纸本)9798350359343
Neural networks with quantized activation functions cannot adapt the quantization at the input of their first layer. Preprocessing is therefore required to adapt the range of input data to the quantization range. Such preprocessing usually includes an activation-wise linear transformation and is steered by the properties of the training set. We suggest to include the linear transform into the training process. Using the Jet Stream Classification task and an evaluation architecture of three quantized dense layers, we document that it improves accuracy, requires the same resources as standard preprocessing, plays a role in network pruning, and is reasonably stable with respect to initialization.
Binary comparator networks have already been used in quasi delay-insensitive (QDI) circuit design for the construction of completion detectors. This paper demonstrates how they can also be utilized to implement a wide...
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ISBN:
(纸本)9798350359343
Binary comparator networks have already been used in quasi delay-insensitive (QDI) circuit design for the construction of completion detectors. This paper demonstrates how they can also be utilized to implement a wide range of Boolean functions for combinational QDI logic blocks. designing combinational logic for QDI circuits poses several challenges because data must be processed in an encoded form (usually dual-rail) and it must be ensured that the resulting circuits do not contain hazards or orphans. These design constraints impose a considerable hardware overhead on the resulting circuits. Hence, over the years numerous design and optimization strategies have been proposed. We show that our comparator-network-based construction approach yields promising results for certain types of functions compared to other common QDI design styles.
This paper explains the background of the well-edge proximity effect (WPE) and sums up its impact on pMOS threshold voltage (V-th) in the following CMOS technologies: 65nm (bulk), 40nm (bulk) from two different vendor...
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ISBN:
(纸本)9798350359343
This paper explains the background of the well-edge proximity effect (WPE) and sums up its impact on pMOS threshold voltage (V-th) in the following CMOS technologies: 65nm (bulk), 40nm (bulk) from two different vendors, 28nm (bulk and FDSOI) and 16nm (FinFET). The results clearly show that WPE cannot be ignored during layout design for any of presented technology. Fortunately, the effect of well-edge proximity is essential at 1 mu m or shorter distances. At longer distances its impact decreases almost to zero. In 40nm technology it can change threshold voltage even by 33 % for IO devices while at 16nm the change will be just 1.87%. Although the technologies are varied in transistor length and process of fabrication the WPE effect remains present.
designing power electronic switches in a timely manner is essential for a wide range of electrical applications. The challenge arises when determining the acceptable design parameters from the product definition space...
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ISBN:
(纸本)9798350359343
designing power electronic switches in a timely manner is essential for a wide range of electrical applications. The challenge arises when determining the acceptable design parameters from the product definition space that lead to a functioning application. Creating a well-defined product definition space can help reduce design cycle time and minimize the risk of design failure or non-compliance with requirements. In response to this, we propose a machine learning-based framework to create this space with substantially less simulations in comparison to exhaustive and optimization-based methods. This is particularly beneficial in higher dimensions where running numerous simulations may not be feasible. We applied this approach to generic silicon power switches within a half-bridge motor drive application simulation, defining borders that closely match-above 98%-to the borders of the product definition space. In this use case, the need for simulations is reduced by a factor of five, while still meeting all operating conditions and requirements.
Small quantized neural networks with strong requirements on throughput and latency can be translated into logic circuits and synthesized by logic design tools. With networks having no state (memory), the circuits are ...
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ISBN:
(纸本)9798350359343
Small quantized neural networks with strong requirements on throughput and latency can be translated into logic circuits and synthesized by logic design tools. With networks having no state (memory), the circuits are combinational. To capture the function of the network (or a part of it) as a logic function, two approaches have been taken. The first one observes the inputs and outputs, while the network predicts a training set, and uses them directly as specification. The response to activation values that have not occurred in the training set remains unspecified. The other approach uses a complete set of activation values at the input of the examined part. We measured accuracy, the influence of logic minimization, and their impact on the final synthesized circuit on dense neural networks in different stages of low-magnitude pruning on the MNIST and JSC datasets. The results show that the first method can be used for functions with fan-in below 10-12 while not working against generalization. We also document the quantitative changes in quantized networks.
Arithmetic circuits form the foundation of modern digital computation, enabling us to conduct precise mathematical operations and drive the digital age. They are integral components in nearly every digital circuit, su...
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ISBN:
(纸本)9798350359343
Arithmetic circuits form the foundation of modern digital computation, enabling us to conduct precise mathematical operations and drive the digital age. They are integral components in nearly every digital circuit, such as processors' arithmetic and logic units. Especially in safety-critical domains like automotive and aviation, the flawless operation of these circuits is of paramount importance. This paper presents a case study involving two variants of Dadda multipliers and assesses their intrinsic reliability when affected by permanent hardware faults. We conducted extensive fault injection campaigns on the circuit models under various datasets, presenting the aggregated statistical errors in the form of the mean absolute error (MAE) for each case. Specifically, we performed fault injection campaigns in which the operands are sourced from trained quantized weights of a convolutional neural network, as well as randomly generated sets of integers. The results not only reveal differences between the two circuits but also show significant variations when different datasets are used in the fault injection campaigns.
The functional safety of implanted medical devices is of high importance. This works presents a novel concept to verify bio-electronicsystems modeling the medical device in connection with the interacting biological ...
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ISBN:
(纸本)9798350332773
The functional safety of implanted medical devices is of high importance. This works presents a novel concept to verify bio-electronicsystems modeling the medical device in connection with the interacting biological system. The concept is applied to a setup consisting of an implanted pacemaker and an interacting organ, the human heart. The resulting model is verified with respect to relevant properties such as the reachability of hazard-related states appearing through the interaction of the bioelectronic system. In contrast to previous contributions this work demonstrates the ability to deterministicly verify bio-electronicsystems containing relevant and detailed models of the interacting biological system.
Recent advances in near-sensor computing have prompted the need to design low-cost digital filters for edge devices. Stochastic computing (SC), leveraging its probabilistic bit-streams, has emerged as a compelling alt...
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ISBN:
(纸本)9798350359343
Recent advances in near-sensor computing have prompted the need to design low-cost digital filters for edge devices. Stochastic computing (SC), leveraging its probabilistic bit-streams, has emerged as a compelling alternative to traditional deterministic computing for filter design. This paper examines error tolerance, area and power efficiency, and accuracy loss in SC-based digital filters. Specifically, we investigate the impact of various stochastic number generators and increased filter complexity on both FIR and IIR filters. Our results indicate that in an error-free environment, SC exhibits a 49% area advantage and a 64% power efficiency improvement, albeit with a slight loss of accuracy, compared to traditional binary implementations. Furthermore, when the input bitstreams are subject to a 2% bit-flip error rate, SC FIR and SC IIR filters have a much smaller performance degradation (1.3X and 1.9X, respectively) than comparable binary filters. In summary, this work provides useful insights into the advantages of stochastic computing in digital filter design, showcasing its robust error resilience, significant area and power efficiency gains, and trade-offs in accuracy compared to traditional binary approaches.
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