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A Common Computational Science Environment for high performance computing Centers

A Common Computational Science Environment for High Performa...

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dod high performance computing modernization program users group

作者： Jerry Clarke John Vines Kelly Kirk Eric Mark Rick Angelini Carrie Spear Nathaniel Waisbrot Joel Martin Ken Leiter Bill Hoffman US Army Research Laboratory Adelphi MD US ARL Lockheed Martin Aberdeen Proving Ground MD USA Kitware Inc Clifton Park NY US

The Computational Sciences Environment (CSE) was developed to provide a standard development platform for data analysis, visualization, and software testing and evaluation. The Classified Data Analysis and Assessment Center (CDAAC), in conjunction with the Computational Sciences and Engineering Branch (CSEB) of the Army Research Laboratory, assembled a set of open source data analysis tools and applications, software management and testing tools, and libraries necessary to run the tools; and made them available as a package called CSE. CSE also provides experimental software builds for users who might need newer features than what is currently available in the release package. The CSE team provides support for developers, the end-user, and distributed development teams. Tests are regularly run on the software, both current and release, and the results are submitted to quality dashboards for review using CTest. CTest is part of an open-source software building tool called CMake. Developers can use CSE as a template and can customize it to meet their specific project goals. CSE provides developers with a common tool set to assist in developing portable high performance computing (HPC) Applications. Development of CSE has been managed through an open-source project management application that provides Software Configuration Management (SCM) integration of the CSE repository, informational wikis, bug tracking, and feature requests. To support distributed development teams, CSE provides project management tools, software repositories, SCM, and online software quality dashboards.

关键词： Software Libraries Data visualization Testing Data analysis US Department of Defense Buildings

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Optimized high-Resolution Simulation of a THz Traveling Wave Tube Amplifier

Optimized High-Resolution Simulation of a THz Traveling Wave...

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dod high performance computing modernization program users group

作者： Spencer E. Olson Nathaniel P. Lockwood Paul D. Gensheimer Directed Energy Directorate (AFRLIRD) US Air Force Research Laboratory Kirtland AFB NM

Modeling of complex systems typically requires many iterations of theoretical design, numerical simulation, and analysis. The goal of this project was to develop an automated optimization framework to optimize a 0.22 THz traveling wave tube (TWT) high-power amplifier design. Applications for such an amplifier include three-dimensional (3D) imaging systems for medical uses, detection of concealed hazardous materials, and high-bandwidth communications. An optimization framework was developed for the dod Supercomputing Resource Center (DSRC) environment to automatically queue and track many simultaneous thousand CPU hour jobs. Results were automatically evaluated, collated, and used to refine simulations, thus saving many man-hours otherwise used for performing parameter scans and analysis. Prior efforts typically required thousands of manually submitted jobs over the course of three years, and resulted in a design that did not meet the desired specifications, e.g., the electron-gun (e-gun) component produced a noisy 4.4 mA, 150 μm diameter electron beam which fed into a 13 dB amplifier that exhibited detrimental backwards-wave oscillations. The automated effort produced thousands of runs over a month and met the design goals with an e-gun providing a low-noise, 10 mA, 100 μm diameter electron beam feeding into a 21 dB amplifier with no backwards-wave oscillations. The work presented here involved thousands of runs consuming around 3.8 million CPU hours. Hence, the near-exclusive access provided by the Capabilities Application Project was critical for the success of this effort.

关键词： Optimization Computational modeling Electron beams Cathodes program processors Optics

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Unitary Quantum Lattice Gas Algorithms for Quantum to Classical Turbulence

Unitary Quantum Lattice Gas Algorithms for Quantum to Classi...

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dod high performance computing modernization program users group

作者： George Vahala Jeffrey Yepez Min Soe Linda Vahala Sean Ziegeler Department of Physics The College of William & Mary Williamsburg VA Department of Mathematics and Physics Rogers State University Claremore OK US Air Force Research Laboratory (AFRL) Hanscom AFB MA Department of Electrical & Computer Engineering Old Dominion University Norfolk VA High Performance Technologies Inc Reston VA

Using a set of interleaved unitary collision-stream operators, a three-dimensional (3D) quantum lattice gas algorithm is devised which, on taking moments, recovers the Gross-Pitaevskii (GP) equation. If a zero-temperature Bose-Einstein condensate (BEC) is trapped in an a magnetic well, the evolution of the ground-state wave function satisfies the scalar GP equation, while if the BEC is trapped in an optical trap the ground-state wave function satisfies spin or GP equations. Quantum turbulence is studied in a scalar GP system on 5,7603 grid yielding not only the classical Kolmogorov k-5/3 cascade but also the quantum vortex k-3 spectrum. For a certain class of initial conditions, one finds an intermittent loss of tangled quantum vortices as the vortex cores attain minimal size, and thus prevent the Kelvin wave cascade (due to helical wave-wave coupling on the vortex). A coupled set of GP equations are solved for spin or BEC. Skrymions, which describe topologically-linked quantum vortices, are examined. One finds, for certain initial conditions that the incompressible kinetic energy spectrum for the condensate component of a vortex ring core rapidly departs from the k-3 linear quantum vortex spectrum.

关键词： Kelvin Equations Mathematical model Kinetic energy Lattices Wave functions Magnetic cores

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Properties of high-performance Capacitor Materials and Nanoscale Electronic Devices

Properties of High-Performance Capacitor Materials and Nanos...

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dod high performance computing modernization program users group

作者： J. Bernholc V. Ranjan X. H. Zheng J. Jiang W. Lu T. A. Abtew P. Boguslawski M. Buongiorno Nardelli V. Meunier Center for High Performance Simulation North Carolina State University Raleigh NC Oak Ridge National Laboratory Oak Ridge TN US Computer Science and Mathematics Division Oak Ridge National Laboratory Oak Ridge TN

Recent advances in theoretical methods combined with the advent of massively parallel supercomputers allow one to reliably simulate the properties of complex materials and device structures from first principles. We describe applications in two general areas: i) novel polymer composites for ultra-high-density capacitors, necessary for pulsed-power applications, such as electric rail guns, power conditioning, and dense electronic circuitry, and ii) electronic properties in nanoelectronic devices, such as graphene nanoribbons and C 60 -based devices. For capacitor materials, polyvinylidene fluoride (PVDF) with a small concentration of chlorotrifluoroethylene (CTFE) has been observed to store very high energy as compared to currently used polymers. We have recently suggested that the ultra-high energy storage is due to an electric-field-induced phase transition from the non-polar α to the polar β-PVDF. We have now extended our investigations to multi-component polymers and also to the initial stages of kinetics. Turning to nanoelectronic materials, we show that devices based on two C 60 molecules can display negative differential resistance at low voltages. We also explore the electronic structure and spin polarization of nitrogen-doped carbon nanoribbons, which are candidate materials for ultra-high-speed nanodevices. We find enhanced N segregation in zigzag nanoribbons, due to interplay between impurity states in the valence bands and the edge states. Spin distribution is significantly affected, even at edges that are quite far from the dopant. We also find that the three armchair nanoribbons (ARs) families, defined by mod (n, 3), behave differently in doping.

关键词： Polymers Electrodes Oscillators Nanoscale devices Electric potential Chemicals

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Mapping Hierarchical Multiple File VHDL Kernels onto an SRC-7 high performance Reconfigurable Computer

Mapping Hierarchical Multiple File VHDL Kernels onto an SRC-...

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dod high performance computing modernization program users group

作者： Gerald R. Morris Khalid H. Abed US Army Engineer Research & Development Center DoD Supercomputing Resource Center (ERDC DSRC) Vicksburg MS Department of Computer Engineering Jackson State University Jackson MS

The increasing computational requirements of today's software systems have led researchers to investigate ways of accelerating military and scientific computing applications. Contemporary field programmable gate arrays (FPGAs) are now equipped with multimillion gate logic fabrics, faster clock rates, reasonably large on-chip memory, and fast I/O resources for off-chip communication. The use of FPGAs as reconfigurable computational units complementing a fixed computational device such as a general-purpose processor (GPP) is the basic idea behind what are known as high performance reconfigurable computers (HPRCs). These exciting architectures allow development of reconfigurable processors that target the computationally intensive parts of a given application. Ideally, one should use a high-level language (HLL) rather than a hardware description language (HDL) to implement HPRC-based applications. However, in order to accelerate some applications, an HDL must be used to design computational kernels. The HPRC used in the joint research project between the U.S. Army Engineer Research and Development Center {dod Supercomputing} Resource Center (ERDC DSRC) and Jackson State University (JSU) employs the SRC Computers' Carte development environment. Carte allows application development using a conventional HLL, an HLL-to-HDL compiler, and custom-built VHDL-based kernels ("user macros" in SRC parlance). Currently, the off-the-shelf Carte mechanism for incorporating user macros does not directly support the common case of a multiple file VHDL hierarchy. This research explores a novel approach that allows multiple file VHDL kernels to be mapped onto the SRC-7 HPRC. The approach facilitates the development of FPGA-based elements via a hybrid technique that uses the Carte HLL-to-HDL compiler in conjunction with multiple file VHDL-based user macros. This paper describes the use of this novel approach to map a parameterized, parallelized, and pipelined FPGA-based sparse matrix vect

关键词： Sparse matrices Hardware Field programmable gate arrays Kernel Hardware design languages Computers

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Design of Very high-Strength Aligned and Interconnected Carbon Nanotube Fibers Based on Molecular Dynamics Simulations

Design of Very High-Strength Aligned and Interconnected Carb...

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dod high performance computing modernization program users group

作者： Charles F. Cornwell Jeffrey B. Allen Charles P. Marsh Thomas A. Carlson Peter B. Stynoski Bradley A. Newcomb Benjamin Masters Robert M. Ebeling Charles R. Welch US Army Engineer Research and Development Center (ERDC) Vicksburg MS

The principal objective of this work is to implement a new material development paradigm using atomistic simulations to guide the molecular design of materials. Traditional empirical macroscopic material development studies omit the fundamental insight needed to understand material behavior at the atomic and molecular levels where material response begins. The new paradigm relies heavily on a tight integration between simulation and experimental efforts to design and process new materials with nanometer-scale precision. Exploiting nanotechnology requires atomic-molecular-level material design and the ability to process these materials with atomic-molecular-level precision. Processing materials with nanoscale precision poses formidable theoretical, computational, and experimental challenges to developing advanced materials. high performance computers and advanced physics-based simulations can complement experimental efforts to design, test, synthesize, and analyze novel materials and innovative structural designs. This method can be applied to a wide range of material designs. As a proof of concept, we began our work on the design of novel carbon nanotube-based materials. The mechanical properties of carbon nanotubes such as low-density, high-stiffness, and exceptional strength make them ideal candidates for reinforcement material in a wide range of high performance composites. Molecular dynamics simulations are used to predict the tensile response of fibers composed of aligned carbon nanotubes with intermolecular bonds of interstitial carbon atoms. The effects of bond density and carbon nanotube length distribution on fiber strength and stiffness are investigated. Results indicate that including cross link atoms between the carbon nanotubes in the strands significantly increases the load transfer between the carbon nanotubes and prevents them from slipping. This increases the elastic modulus and yield strength of the fibers by an order-of-magnitude. Carbon nanotube-

关键词： Carbon nanotubes Materials Strain Carbon Atomic measurements Load modeling

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Accelerating a Sparse Matrix Iterative Solver Using a high performance Reconfigurable Computer

Accelerating a Sparse Matrix Iterative Solver Using a High P...

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dod high performance computing modernization program users group

作者： Gerald R. Morris Ricky Y. McGruder Khalid H. Abed US Army Engineer Research & Development Center DoD Supercomputing Resource Center (ERDC DSRC) Vicksburg MS Department of Computer Engineering Jackson State University Jackson MS

high performance reconfigurable computers (HPRCs), which combine general-purpose processors (GPPs) and field programmable gate arrays (FPGAs), are now commercially available. These interesting architectures allow for the creation of reconfigurable processors. HPRCs have already been used to accelerate integer and fixed-point applications. However, extensive parallelism and deeply pipelined floating-point cores are necessary to make MHz-scale FPGAs competitive with GHz-scale GPPs, thus making it difficult to accelerate certain kinds of floating-point kernels. Kernels with variable length nested loops, e.g., sparse matrix-vector multiply, have been problematic because of the loop-carried dependence associated with the pipelined floating-point units. While hardware description language (HDL)-based kernels have shown moderate success in addressing this problem, the use of a high-level language (HLL)-based approach to accelerate such applications has been rather elusive. If HPRCs are to become a part of mainstream military and scientific computing, we should emphasize the use of HLL-based programming, whenever possible, rather than HDL-based hardware design. The primary reason is the increased programmer productivity associated with HLLs when compared with HDLs. For example, the floating-point addition statement z = x+y, a single line in an HLL, corresponds to hundreds of lines of HDL. In this paper, we describe the design and implementation of a sparse matrix Jacobi processor to solve systems of linear equations, Ax=b. The parallelized, deeply pipelined, IEEE-754-compliant 32-bit floating-point sparse matrix Jacobi iterative solver runs on a contemporary HPRC. The FPGA-based components are implemented using only an HLL (the C programming language) and the Carte HLL-to-HDL compiler. An HLL-based streaming accumulator allows for the implementation of fully pipelined loops and results in a 2.5-fold wall clock runtime speedup when compared with an equivalent software-only i

关键词： Jacobian matrices Sparse matrices program processors Field programmable gate arrays Kernel Hardware Computers

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Large-Scale Computations of Unsteady Forces on Marine Vehicles

Large-Scale Computations of Unsteady Forces on Marine Vehicl...

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dod high performance computing modernization program users group

作者： Peter Chang Minyee Jiang Dory Lummer Krishnan Mahesh Carderock Division (NSWCCD) US Naval Surface Warfare Center West Bethesda MD Department of Aerospace Engineering and Mechanics University of Minnesota Minneapolis MN

Despite efforts to maintain streamlined shapes for minimal resistance and noise, US Navy marine vehicles oftentimes must have bluff body geometries or must operate in off-design modes. These situations produce separated flows that are unsteady. At large scales the flow unsteadiness may be the cause of structural concerns while the entire range of fluid dynamic scales, from large to small, may be the cause of unwanted hydro-acoustic radiated noise. Large-eddy simulations (LES) are a class of fluid flow solvers that resolve the energy-containing scales of attached and separated flows, potentially providing the velocity field forcing functions for structural and hydro-acoustics analyses. LES have strict temporal and spatial grid spacing requirements and in order to resolve the energy-containing turbulence scales at practical flow velocities, the problem sizes and run times can be quite impressive. The objective of this Challenge Project is to apply LES to several problems of urgent US Navy need that have heretofore been considered too large to solve in a timely fashion. The first of these problems occurs when a marine vehicle, translating forward, must stop suddenly. This entails reversing the rotation of the propeller in a maneuver called crashback. This generates the largest forces that a propeller will undergo in its lifetime, and therefore, prediction of the forces and determination of procedures to reduce the forces, are of utmost importance. Using LES we have been able to uncover and verify the physics of force generation. With this Challenge Project, methodologies are being developed for one-way coupling between fluid flow and structural calculations that entail 300,000+ hours of CPU time. Another problem that is being tackled with the help of the Challenge grant is flow about the Advanced SEAL Delivery System (ASDS). This is a challenging geometry as it has both complex geometry and is a high-Reynolds number attached flow. Thus, the grid quality and size are im

关键词： Propellers Computer crashes Blades program processors Mathematical model Torque Computational modeling

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high-resolution simulations of internal gravity-wave fine structure interactions and implications for atmospheric turbulence forecasting

High-resolution simulations of internal gravity-wave fine st...

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2009 dod high performance computing modernization program - users group conference, hpcmp-ugc 2009

作者： Werne, Joseph Fritts, David C. Wang, Ling Northwest Research Associates Colorado Research Associates Division Boulder CO United States

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Using star-P® on dod high performance computing systems

Using star-P® on DoD high performance computing systems

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2009 dod high performance computing modernization program - users group conference, hpcmp-ugc 2009

作者： Elton, Bracy H. Samsi, Siddharth Smith, Harrison Ben Humphrey, Laura Ahalt, Stanley Chalker, Alan Srivastava, Niraj Abdullah, Aquil H. Boyle, Patrick Ohio Supercomputer Center Columbus OH United States High Performance Technologies Inc. United States Interactive Supercomputing Inc. Waltham MA United States

ISBN: (纸本)9780769539461

This paper provides a step-by-step demonstration of a Very high Level Language system, Star-P, on Department of Defense (dod) high performance computing (HPC) systems. Specifically, we demonstrate how to effect parallel computing in MATLAB and Python via Star-P on the dod Supercomputing Resource Center (DSRC) Army Research Laboratory (ARL) 4,488-core Intel Woodcrest MJM system. We demonstrate how to run various Star-P/MATLAB and Star-P/Python programs in parallel on the ARL DSRC MJM system. The results will focus on the use of Star-P software platform and how it delivers mission tempo by enabling rapid application prototyping and allowing transparent use of DSRC HPC resources from familiar desktop environments, such as Microsoft Windows and Linux. © 2010 IEEE.

关键词： Stars

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